prev_cmp_uart.map.qmsg

vhdl书写uart代码,经验证功能非常的全.

{ "Info" "ISGN_START_ELABORATION_TOP" "uart_top " "Info: Elaborating entity \"uart_top\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "baudrate_generator baudrate_generator:U_BG " "Info: Elaborating entity \"baudrate_generator\" for hierarchy \"baudrate_generator:U_BG\"" {  } { { "uart_top.vhd" "U_BG" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_top.vhd" 191 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "switch_bus switch_bus:U_BusSwitch " "Info: Elaborating entity \"switch_bus\" for hierarchy \"switch_bus:U_BusSwitch\"" {  } { { "uart_top.vhd" "U_BusSwitch" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_top.vhd" 200 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_core uart_core:U_Core " "Info: Elaborating entity \"uart_core\" for hierarchy \"uart_core:U_Core\"" {  } { { "uart_top.vhd" "U_Core" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_top.vhd" 208 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "send_buf uart_core.vhd(267) " "Warning (10492): VHDL Process Statement warning at uart_core.vhd(267): signal \"send_buf\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 267 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:U_Counter " "Info: Elaborating entity \"counter\" for hierarchy \"counter:U_Counter\"" {  } { { "uart_top.vhd" "U_Counter" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_top.vhd" 232 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "ce counter.vhd(32) " "Warning (10492): VHDL Process Statement warning at counter.vhd(32): signal \"ce\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "counter.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/counter.vhd" 32 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "switch switch:U_CounterClkSwitch " "Info: Elaborating entity \"switch\" for hierarchy \"switch:U_CounterClkSwitch\"" {  } { { "uart_top.vhd" "U_CounterClkSwitch" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_top.vhd" 240 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "detector detector:U_Detector " "Info: Elaborating entity \"detector\" for hierarchy \"detector:U_Detector\"" {  } { { "uart_top.vhd" "U_Detector" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_top.vhd" 248 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "parity_verifier parity_verifier:U_ParityVerifier " "Info: Elaborating entity \"parity_verifier\" for hierarchy \"parity_verifier:U_ParityVerifier\"" {  } { { "uart_top.vhd" "U_ParityVerifier" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_top.vhd" 256 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shift_register shift_register:U_SR " "Info: Elaborating entity \"shift_register\" for hierarchy \"shift_register:U_SR\"" {  } { { "uart_top.vhd" "U_SR" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_top.vhd" 270 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_OPT_PROTECT_A_CLOCK_MUX" "" "Info: Clock multiplexers have been protected" {  } {  } 0 0 "Clock multiplexers have been protected" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|uart_top\|uart_core:U_Core\|state 6 " "Info: State machine \"\|uart_top\|uart_core:U_Core\|state\" contains 6 states" {  } { { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 50 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|uart_top\|uart_core:U_Core\|state " "Info: Selected Auto state machine encoding method for state machine \"\|uart_top\|uart_core:U_Core\|state\"" {  } { { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 50 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|uart_top\|uart_core:U_Core\|state " "Info: Encoding result for state machine \"\|uart_top\|uart_core:U_Core\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "6 " "Info: Completed encoding using 6 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "uart_core:U_Core\|state.uart_end_recv " "Info: Encoded state bit \"uart_core:U_Core\|state.uart_end_recv\"" {  } { { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 50 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "uart_core:U_Core\|state.uart_recv " "Info: Encoded state bit \"uart_core:U_Core\|state.uart_recv\"" {  } { { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 50 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "uart_core:U_Core\|state.uart_end_send " "Info: Encoded state bit \"uart_core:U_Core\|state.uart_end_send\"" {  } { { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 50 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "uart_core:U_Core\|state.uart_send " "Info: Encoded state bit \"uart_core:U_Core\|state.uart_send\"" {  } { { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 50 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "uart_core:U_Core\|state.uart_load " "Info: Encoded state bit \"uart_core:U_Core\|state.uart_load\"" {  } { { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 50 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "uart_core:U_Core\|state.uart_idle " "Info: Encoded state bit \"uart_core:U_Core\|state.uart_idle\"" {  } { { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 50 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_top\|uart_core:U_Core\|state.uart_idle 000000 " "Info: State \"\|uart_top\|uart_core:U_Core\|state.uart_idle\" uses code string \"000000\"" {  } { { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 50 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_top\|uart_core:U_Core\|state.uart_load 000011 " "Info: State \"\|uart_top\|uart_core:U_Core\|state.uart_load\" uses code string \"000011\"" {  } { { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 50 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_top\|uart_core:U_Core\|state.uart_send 000101 " "Info: State \"\|uart_top\|uart_core:U_Core\|state.uart_send\" uses code string \"000101\"" {  } { { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 50 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_top\|uart_core:U_Core\|state.uart_end_send 001001 " "Info: State \"\|uart_top\|uart_core:U_Core\|state.uart_end_send\" uses code string \"001001\"" {  } { { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 50 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_top\|uart_core:U_Core\|state.uart_recv 010001 " "Info: State \"\|uart_top\|uart_core:U_Core\|state.uart_recv\" uses code string \"010001\"" {  } { { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 50 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_top\|uart_core:U_Core\|state.uart_end_recv 100001 " "Info: State \"\|uart_top\|uart_core:U_Core\|state.uart_end_recv\" uses code string \"100001\"" {  } { { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 50 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0}  } { { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 50 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "shift_register.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/shift_register.vhd" 15 -1 0 } } { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 20 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "212 " "Info: Implemented 212 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "12 " "Info: Implemented 12 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "188 " "Info: Implemented 188 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "153 " "Info: Allocated 153 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 22 18:00:30 2007 " "Info: Processing ended: Thu Nov 22 18:00:30 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}