📄 prev_cmp_uart.map.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 22 18:00:24 2007 " "Info: Processing started: Thu Nov 22 18:00:24 2007" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off uart -c uart " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off uart -c uart" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "UART_PACKAGE.vhd 2 0 " "Info: Found 2 design units, including 0 entities, in source file UART_PACKAGE.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 UART_PACKAGE " "Info: Found design unit 1: UART_PACKAGE" { } { { "UART_PACKAGE.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/UART_PACKAGE.vhd" 6 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 UART_PACKAGE-body " "Info: Found design unit 2: UART_PACKAGE-body" { } { { "UART_PACKAGE.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/UART_PACKAGE.vhd" 65 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_top.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file uart_top.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 uart_top-uart_top " "Info: Found design unit 1: uart_top-uart_top" { } { { "uart_top.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_top.vhd" 42 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 uart_top " "Info: Found entity 1: uart_top" { } { { "uart_top.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_top.vhd" 5 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_top_tb.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file uart_top_tb.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 uart_top_tb-TB_ARCHITECTURE " "Info: Found design unit 1: uart_top_tb-TB_ARCHITECTURE" { } { { "uart_top_tb.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_top_tb.vhd" 19 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 TESTBENCH_FOR_uart_top " "Info: Found design unit 2: TESTBENCH_FOR_uart_top" { } { { "uart_top_tb.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_top_tb.vhd" 133 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 uart_top_tb " "Info: Found entity 1: uart_top_tb" { } { { "uart_top_tb.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_top_tb.vhd" 7 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "baudrate_generator.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file baudrate_generator.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 baudrate_generator-baudrate_generator " "Info: Found design unit 1: baudrate_generator-baudrate_generator" { } { { "baudrate_generator.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/baudrate_generator.vhd" 24 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 baudrate_generator " "Info: Found entity 1: baudrate_generator" { } { { "baudrate_generator.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/baudrate_generator.vhd" 7 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_core.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file uart_core.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 uart_core-uart_core " "Info: Found design unit 1: uart_core-uart_core" { } { { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 47 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 uart_core " "Info: Found entity 1: uart_core" { } { { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 6 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "baudrate_generator_TB.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file baudrate_generator_TB.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 baudrate_generator_tb-TB_ARCHITECTURE " "Info: Found design unit 1: baudrate_generator_tb-TB_ARCHITECTURE" { } { { "baudrate_generator_TB.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/baudrate_generator_TB.vhd" 34 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 TESTBENCH_FOR_baudrate_generator " "Info: Found design unit 2: TESTBENCH_FOR_baudrate_generator" { } { { "baudrate_generator_TB.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/baudrate_generator_TB.vhd" 98 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 baudrate_generator_tb " "Info: Found entity 1: baudrate_generator_tb" { } { { "baudrate_generator_TB.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/baudrate_generator_TB.vhd" 27 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter-counter " "Info: Found design unit 1: counter-counter" { } { { "counter.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/counter.vhd" 17 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 counter " "Info: Found entity 1: counter" { } { { "counter.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/counter.vhd" 5 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter_TB.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file counter_TB.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter_tb-TB_ARCHITECTURE " "Info: Found design unit 1: counter_tb-TB_ARCHITECTURE" { } { { "counter_TB.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/counter_TB.vhd" 32 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 TESTBENCH_FOR_counter " "Info: Found design unit 2: TESTBENCH_FOR_counter" { } { { "counter_TB.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/counter_TB.vhd" 91 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 counter_tb " "Info: Found entity 1: counter_tb" { } { { "counter_TB.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/counter_TB.vhd" 26 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "detector.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file detector.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 detector-detector " "Info: Found design unit 1: detector-detector" { } { { "detector.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/detector.vhd" 16 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 detector " "Info: Found entity 1: detector" { } { { "detector.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/detector.vhd" 6 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "detector_TB.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file detector_TB.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 detector_tb-TB_ARCHITECTURE " "Info: Found design unit 1: detector_tb-TB_ARCHITECTURE" { } { { "detector_TB.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/detector_TB.vhd" 30 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 TESTBENCH_FOR_detector " "Info: Found design unit 2: TESTBENCH_FOR_detector" { } { { "detector_TB.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/detector_TB.vhd" 96 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 detector_tb " "Info: Found entity 1: detector_tb" { } { { "detector_TB.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/detector_TB.vhd" 27 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "parity_verifier.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file parity_verifier.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 parity_verifier-parity_verifier " "Info: Found design unit 1: parity_verifier-parity_verifier" { } { { "parity_verifier.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/parity_verifier.vhd" 20 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 parity_verifier " "Info: Found entity 1: parity_verifier" { } { { "parity_verifier.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/parity_verifier.vhd" 7 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "parity_verifier_TB.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file parity_verifier_TB.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 parity_verifier_tb-TB_ARCHITECTURE " "Info: Found design unit 1: parity_verifier_tb-TB_ARCHITECTURE" { } { { "parity_verifier_TB.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/parity_verifier_TB.vhd" 34 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 TESTBENCH_FOR_parity_verifier " "Info: Found design unit 2: TESTBENCH_FOR_parity_verifier" { } { { "parity_verifier_TB.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/parity_verifier_TB.vhd" 80 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 parity_verifier_tb " "Info: Found entity 1: parity_verifier_tb" { } { { "parity_verifier_TB.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/parity_verifier_TB.vhd" 27 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shift_register.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file shift_register.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 shift_register-shift_register " "Info: Found design unit 1: shift_register-shift_register" { } { { "shift_register.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/shift_register.vhd" 21 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 shift_register " "Info: Found entity 1: shift_register" { } { { "shift_register.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/shift_register.vhd" 5 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shift_register_TB.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file shift_register_TB.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 shift_register_tb-TB_ARCHITECTURE " "Info: Found design unit 1: shift_register_tb-TB_ARCHITECTURE" { } { { "shift_register_TB.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/shift_register_TB.vhd" 32 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 TESTBENCH_FOR_shift_register " "Info: Found design unit 2: TESTBENCH_FOR_shift_register" { } { { "shift_register_TB.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/shift_register_TB.vhd" 96 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 shift_register_tb " "Info: Found entity 1: shift_register_tb" { } { { "shift_register_TB.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/shift_register_TB.vhd" 26 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "switch.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file switch.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 switch-switch " "Info: Found design unit 1: switch-switch" { } { { "switch.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/switch.vhd" 16 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 switch " "Info: Found entity 1: switch" { } { { "switch.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/switch.vhd" 5 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "switch_bus.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file switch_bus.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 switch_bus-switch_bus " "Info: Found design unit 1: switch_bus-switch_bus" { } { { "switch_bus.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/switch_bus.vhd" 19 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 switch_bus " "Info: Found entity 1: switch_bus" { } { { "switch_bus.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/switch_bus.vhd" 6 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "switch_bus_TB.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file switch_bus_TB.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 switch_bus_tb-TB_ARCHITECTURE " "Info: Found design unit 1: switch_bus_tb-TB_ARCHITECTURE" { } { { "switch_bus_TB.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/switch_bus_TB.vhd" 32 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 TESTBENCH_FOR_switch_bus " "Info: Found design unit 2: TESTBENCH_FOR_switch_bus" { } { { "switch_bus_TB.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/switch_bus_TB.vhd" 81 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 switch_bus_tb " "Info: Found entity 1: switch_bus_tb" { } { { "switch_bus_TB.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/switch_bus_TB.vhd" 26 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
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