uart.map.rpt

vhdl书写uart代码,经验证功能非常的全.

Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_core:U_Core ;
+----------------+-------+--------------------------------------+
; Parameter Name ; Value ; Type                                 ;
+----------------+-------+--------------------------------------+
; data_bit       ; 8     ; Signed Integer                       ;
; total_bit      ; 10    ; Signed Integer                       ;
; parity_rule    ; NONE  ; Enumerated                           ;
+----------------+-------+--------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------+
; Parameter Settings for User Entity Instance: counter:U_Counter ;
+----------------+-------+---------------------------------------+
; Parameter Name ; Value ; Type                                  ;
+----------------+-------+---------------------------------------+
; max_count      ; 10    ; Signed Integer                        ;
+----------------+-------+---------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: parity_verifier:U_ParityVerifier ;
+----------------+-------+------------------------------------------------------+
; Parameter Name ; Value ; Type                                                 ;
+----------------+-------+------------------------------------------------------+
; data_length    ; 8     ; Signed Integer                                       ;
; parity_rule    ; NONE  ; Enumerated                                           ;
+----------------+-------+------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: shift_register:U_SR ;
+----------------+-------+-----------------------------------------+
; Parameter Name ; Value ; Type                                    ;
+----------------+-------+-----------------------------------------+
; total_bit      ; 10    ; Signed Integer                          ;
+----------------+-------+-----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Thu Nov 22 18:00:35 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off uart -c uart
Info: Found 2 design units, including 0 entities, in source file UART_PACKAGE.vhd
    Info: Found design unit 1: UART_PACKAGE
    Info: Found design unit 2: UART_PACKAGE-body
Info: Found 2 design units, including 1 entities, in source file uart_top.vhd
    Info: Found design unit 1: uart_top-uart_top
    Info: Found entity 1: uart_top
Info: Found 3 design units, including 1 entities, in source file uart_top_tb.vhd
    Info: Found design unit 1: uart_top_tb-TB_ARCHITECTURE
    Info: Found design unit 2: TESTBENCH_FOR_uart_top
    Info: Found entity 1: uart_top_tb
Info: Found 2 design units, including 1 entities, in source file baudrate_generator.vhd
    Info: Found design unit 1: baudrate_generator-baudrate_generator
    Info: Found entity 1: baudrate_generator
Info: Found 2 design units, including 1 entities, in source file uart_core.vhd
    Info: Found design unit 1: uart_core-uart_core
    Info: Found entity 1: uart_core
Info: Found 3 design units, including 1 entities, in source file baudrate_generator_TB.vhd
    Info: Found design unit 1: baudrate_generator_tb-TB_ARCHITECTURE
    Info: Found design unit 2: TESTBENCH_FOR_baudrate_generator
    Info: Found entity 1: baudrate_generator_tb
Info: Found 2 design units, including 1 entities, in source file counter.vhd
    Info: Found design unit 1: counter-counter
    Info: Found entity 1: counter
Info: Found 3 design units, including 1 entities, in source file counter_TB.vhd
    Info: Found design unit 1: counter_tb-TB_ARCHITECTURE
    Info: Found design unit 2: TESTBENCH_FOR_counter
    Info: Found entity 1: counter_tb
Info: Found 2 design units, including 1 entities, in source file detector.vhd
    Info: Found design unit 1: detector-detector
    Info: Found entity 1: detector
Info: Found 3 design units, including 1 entities, in source file detector_TB.vhd
    Info: Found design unit 1: detector_tb-TB_ARCHITECTURE
    Info: Found design unit 2: TESTBENCH_FOR_detector
    Info: Found entity 1: detector_tb
Info: Found 2 design units, including 1 entities, in source file parity_verifier.vhd
    Info: Found design unit 1: parity_verifier-parity_verifier
    Info: Found entity 1: parity_verifier
Info: Found 3 design units, including 1 entities, in source file parity_verifier_TB.vhd
    Info: Found design unit 1: parity_verifier_tb-TB_ARCHITECTURE
    Info: Found design unit 2: TESTBENCH_FOR_parity_verifier
    Info: Found entity 1: parity_verifier_tb
Info: Found 2 design units, including 1 entities, in source file shift_register.vhd
    Info: Found design unit 1: shift_register-shift_register
    Info: Found entity 1: shift_register
Info: Found 3 design units, including 1 entities, in source file shift_register_TB.vhd
    Info: Found design unit 1: shift_register_tb-TB_ARCHITECTURE
    Info: Found design unit 2: TESTBENCH_FOR_shift_register
    Info: Found entity 1: shift_register_tb
Info: Found 2 design units, including 1 entities, in source file switch.vhd
    Info: Found design unit 1: switch-switch
    Info: Found entity 1: switch
Info: Found 2 design units, including 1 entities, in source file switch_bus.vhd
    Info: Found design unit 1: switch_bus-switch_bus
    Info: Found entity 1: switch_bus
Info: Found 3 design units, including 1 entities, in source file switch_bus_TB.vhd
    Info: Found design unit 1: switch_bus_tb-TB_ARCHITECTURE
    Info: Found design unit 2: TESTBENCH_FOR_switch_bus
    Info: Found entity 1: switch_bus_tb
Info: Elaborating entity "uart_top" for the top level hierarchy
Info: Elaborating entity "baudrate_generator" for hierarchy "baudrate_generator:U_BG"
Info: Elaborating entity "switch_bus" for hierarchy "switch_bus:U_BusSwitch"
Info: Elaborating entity "uart_core" for hierarchy "uart_core:U_Core"
Warning (10492): VHDL Process Statement warning at uart_core.vhd(267): signal "send_buf" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Elaborating entity "counter" for hierarchy "counter:U_Counter"
Warning (10492): VHDL Process Statement warning at counter.vhd(32): signal "ce" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Elaborating entity "switch" for hierarchy "switch:U_CounterClkSwitch"
Info: Elaborating entity "detector" for hierarchy "detector:U_Detector"
Info: Elaborating entity "parity_verifier" for hierarchy "parity_verifier:U_ParityVerifier"
Info: Elaborating entity "shift_register" for hierarchy "shift_register:U_SR"
Info: Clock multiplexers have been protected
Info: State machine "|uart_top|uart_core:U_Core|state" contains 6 states
Info: Selected Auto state machine encoding method for state machine "|uart_top|uart_core:U_Core|state"
Info: Encoding result for state machine "|uart_top|uart_core:U_Core|state"
    Info: Completed encoding using 6 state bits
        Info: Encoded state bit "uart_core:U_Core|state.uart_end_recv"
        Info: Encoded state bit "uart_core:U_Core|state.uart_recv"
        Info: Encoded state bit "uart_core:U_Core|state.uart_end_send"
        Info: Encoded state bit "uart_core:U_Core|state.uart_send"
        Info: Encoded state bit "uart_core:U_Core|state.uart_load"
        Info: Encoded state bit "uart_core:U_Core|state.uart_idle"
    Info: State "|uart_top|uart_core:U_Core|state.uart_idle" uses code string "000000"
    Info: State "|uart_top|uart_core:U_Core|state.uart_load" uses code string "000011"
    Info: State "|uart_top|uart_core:U_Core|state.uart_send" uses code string "000101"
    Info: State "|uart_top|uart_core:U_Core|state.uart_end_send" uses code string "001001"
    Info: State "|uart_top|uart_core:U_Core|state.uart_recv" uses code string "010001"
    Info: State "|uart_top|uart_core:U_Core|state.uart_end_recv" uses code string "100001"
Info: Registers with preset signals will power-up high
Info: Implemented 212 device resources after synthesis - the final resource count might be different
    Info: Implemented 12 input pins
    Info: Implemented 12 output pins
    Info: Implemented 188 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Allocated 154 megabytes of memory during processing
    Info: Processing ended: Thu Nov 22 18:00:40 2007
    Info: Elapsed time: 00:00:05