uart.fit.rpt

vhdl书写uart代码,经验证功能非常的全.

; 8                                               ; 2                            ;
; 9                                               ; 0                            ;
; 10                                              ; 3                            ;
; 11                                              ; 1                            ;
; 12                                              ; 1                            ;
+-------------------------------------------------+------------------------------+


+-----------------------------------------------------------------------------+
; LAB Distinct Inputs                                                         ;
+----------------------------------------------+------------------------------+
; Number of Distinct Inputs  (Average = 10.60) ; Number of LABs  (Total = 20) ;
+----------------------------------------------+------------------------------+
; 0                                            ; 0                            ;
; 1                                            ; 0                            ;
; 2                                            ; 0                            ;
; 3                                            ; 0                            ;
; 4                                            ; 1                            ;
; 5                                            ; 0                            ;
; 6                                            ; 4                            ;
; 7                                            ; 1                            ;
; 8                                            ; 0                            ;
; 9                                            ; 1                            ;
; 10                                           ; 2                            ;
; 11                                           ; 5                            ;
; 12                                           ; 2                            ;
; 13                                           ; 1                            ;
; 14                                           ; 0                            ;
; 15                                           ; 0                            ;
; 16                                           ; 1                            ;
; 17                                           ; 0                            ;
; 18                                           ; 0                            ;
; 19                                           ; 1                            ;
; 20                                           ; 0                            ;
; 21                                           ; 1                            ;
+----------------------------------------------+------------------------------+


+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Passive Serial           ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Thu Nov 22 18:00:41 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off uart -c uart
Info: Selected device EPM240T100C5 for design "uart"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240T100I5 is compatible
    Info: Device EPM570T100C5 is compatible
    Info: Device EPM570T100I5 is compatible
Warning: No exact pin location assignment(s) for 24 pins of 24 total pins
    Info: Pin send_over not assigned to an exact location on the device
    Info: Pin error not assigned to an exact location on the device
    Info: Pin recv not assigned to an exact location on the device
    Info: Pin recv_bus[0] not assigned to an exact location on the device
    Info: Pin recv_bus[1] not assigned to an exact location on the device
    Info: Pin recv_bus[2] not assigned to an exact location on the device
    Info: Pin recv_bus[3] not assigned to an exact location on the device
    Info: Pin recv_bus[4] not assigned to an exact location on the device
    Info: Pin recv_bus[5] not assigned to an exact location on the device
    Info: Pin recv_bus[6] not assigned to an exact location on the device
    Info: Pin recv_bus[7] not assigned to an exact location on the device
    Info: Pin TxD not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
    Info: Pin reset_n not assigned to an exact location on the device
    Info: Pin send not assigned to an exact location on the device
    Info: Pin RxD not assigned to an exact location on the device
    Info: Pin send_bus[5] not assigned to an exact location on the device
    Info: Pin send_bus[4] not assigned to an exact location on the device
    Info: Pin send_bus[3] not assigned to an exact location on the device
    Info: Pin send_bus[6] not assigned to an exact location on the device
    Info: Pin send_bus[0] not assigned to an exact location on the device
    Info: Pin send_bus[7] not assigned to an exact location on the device
    Info: Pin send_bus[2] not assigned to an exact location on the device
    Info: Pin send_bus[1] not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted some destinations of signal "clk" to use Global clock in PIN 14
    Info: Destination "switch:U_SRClkSwitch|dout" may be non-global or may not use global clock
    Info: Destination "switch:U_CounterClkSwitch|dout" may be non-global or may not use global clock
Info: Automatically promoted signal "switch:U_CounterClkSwitch|dout" to use Global clock
Info: Automatically promoted signal "switch:U_SRClkSwitch|dout" to use Global clock
Info: Automatically promoted some destinations of signal "reset_n" to use Global clock in PIN 12
    Info: Destination "shift_register:U_SR|shift_regs[0]" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 22 (unused VREF, 3.30 VCCIO, 10 input, 12 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  36 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  42 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:01
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to pin delay of 3.508 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X2_Y1; Fanout = 1; REG Node = 'shift_register:U_SR|dout'
    Info: 2: + IC(0.000 ns) + CELL(0.595 ns) = 0.595 ns; Loc. = LAB_X2_Y1; Fanout = 1; COMB Node = 'switch:U_TXDSwitch|dout~2'
    Info: 3: + IC(0.591 ns) + CELL(2.322 ns) = 3.508 ns; Loc. = PIN_26; Fanout = 0; PIN Node = 'TxD'
    Info: Total cell delay = 2.917 ns ( 83.15 % )
    Info: Total interconnect delay = 0.591 ns ( 16.85 % )
Info: Fitter routing operations beginning
Warning: 13 (of 448) connections in the design require a large routing delay to achieve hold requirements. Please check the circuit's timing constraints and clocking methodology, especially multicycles and gated clocks.
    Info: Found 13 Registers with very high hold time requirements
        Info: Node "uart_core:U_Core|recv"
        Info: Node "uart_core:U_Core|recv_bus[4]"
        Info: Node "uart_core:U_Core|sel_out"
        Info: Node "uart_core:U_Core|state.uart_recv"
        Info: Node "baudrate_generator:U_BG|\main:clk_count[7]"
        Info: Node "baudrate_generator:U_BG|\main:clk