uart.tan.rpt

vhdl书写uart代码,经验证功能非常的全.

; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM240T100C5       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                    ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------+---------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                        ; To                                          ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------+---------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 80.61 MHz ( period = 12.405 ns )                    ; counter:U_Counter|overflow                  ; uart_core:U_Core|si_count[2]                ; clk        ; clk      ; None                        ; None                      ; 5.017 ns                ;
; N/A                                     ; 80.61 MHz ( period = 12.405 ns )                    ; counter:U_Counter|overflow                  ; uart_core:U_Core|si_count[1]                ; clk        ; clk      ; None                        ; None                      ; 5.017 ns                ;
; N/A                                     ; 80.61 MHz ( period = 12.405 ns )                    ; counter:U_Counter|overflow                  ; uart_core:U_Core|si_count[0]                ; clk        ; clk      ; None                        ; None                      ; 5.017 ns                ;
; N/A                                     ; 80.61 MHz ( period = 12.405 ns )                    ; counter:U_Counter|overflow                  ; uart_core:U_Core|si_count[3]                ; clk        ; clk      ; None                        ; None                      ; 5.017 ns                ;
; N/A                                     ; 82.47 MHz ( period = 12.125 ns )                    ; counter:U_Counter|overflow                  ; uart_core:U_Core|ce_parts                   ; clk        ; clk      ; None                        ; None                      ; 4.737 ns                ;
; N/A                                     ; 82.82 MHz ( period = 12.075 ns )                    ; counter:U_Counter|overflow                  ; uart_core:U_Core|state.uart_recv            ; clk        ; clk      ; None                        ; None                      ; 4.687 ns                ;
; N/A                                     ; 83.82 MHz ( period = 11.930 ns )                    ; counter:U_Counter|overflow                  ; uart_core:U_Core|sel_clk                    ; clk        ; clk      ; None                        ; None                      ; 4.542 ns                ;
; N/A                                     ; 86.22 MHz ( period = 11.598 ns )                    ; counter:U_Counter|overflow                  ; uart_core:U_Core|sel_out                    ; clk        ; clk      ; None                        ; None                      ; 4.210 ns                ;
; N/A                                     ; 87.09 MHz ( period = 11.483 ns )                    ; counter:U_Counter|overflow                  ; uart_core:U_Core|recv_bus[0]                ; clk        ; clk      ; None                        ; None                      ; 4.095 ns                ;
; N/A                                     ; 87.09 MHz ( period = 11.483 ns )                    ; counter:U_Counter|overflow                  ; uart_core:U_Core|recv_bus[1]                ; clk        ; clk      ; None                        ; None                      ; 4.095 ns                ;
; N/A                                     ; 87.09 MHz ( period = 11.483 ns )                    ; counter:U_Counter|overflow                  ; uart_core:U_Core|recv_bus[2]                ; clk        ; clk      ; None                        ; None                      ; 4.095 ns                ;
; N/A                                     ; 87.09 MHz ( period = 11.483 ns )                    ; counter:U_Counter|overflow                  ; uart_core:U_Core|recv_bus[3]                ; clk        ; clk      ; None                        ; None                      ; 4.095 ns                ;
; N/A                                     ; 87.10 MHz ( period = 11.481 ns )                    ; counter:U_Counter|overflow                  ; uart_core:U_Core|recv_bus[4]                ; clk        ; clk      ; None                        ; None                      ; 4.093 ns                ;
; N/A                                     ; 87.10 MHz ( period = 11.481 ns )                    ; counter:U_Counter|overflow                  ; uart_core:U_Core|recv_bus[5]                ; clk        ; clk      ; None                        ; None                      ; 4.093 ns                ;
; N/A                                     ; 87.10 MHz ( period = 11.481 ns )                    ; counter:U_Counter|overflow                  ; uart_core:U_Core|recv_bus[6]                ; clk        ; clk      ; None                        ; None                      ; 4.093 ns                ;
; N/A                                     ; 87.10 MHz ( period = 11.481 ns )                    ; counter:U_Counter|overflow                  ; uart_core:U_Core|recv_bus[7]                ; clk        ; clk      ; None                        ; None                      ; 4.093 ns                ;
; N/A                                     ; 87.91 MHz ( period = 11.375 ns )                    ; counter:U_Counter|overflow                  ; uart_core:U_Core|state.uart_load            ; clk        ; clk      ; None                        ; None                      ; 3.987 ns                ;
; N/A                                     ; 88.87 MHz ( period = 11.253 ns )                    ; counter:U_Counter|overflow                  ; uart_core:U_Core|reset_parts                ; clk        ; clk      ; None                        ; None                      ; 3.865 ns                ;
; N/A                                     ; 89.68 MHz ( period = 11.151 ns )                    ; counter:U_Counter|overflow                  ; uart_core:U_Core|sel_si                     ; clk        ; clk      ; None                        ; None                      ; 3.763 ns                ;
; N/A                                     ; 91.84 MHz ( period = 10.888 ns )                    ; counter:U_Counter|count[3]                  ; counter:U_Counter|count[22]                 ; clk        ; clk      ; None                        ; None                      ; 9.202 ns                ;
; N/A                                     ; 92.84 MHz ( period = 10.771 ns )                    ; counter:U_Counter|overflow                  ; uart_core:U_Core|send_over                  ; clk        ; clk      ; None                        ; None                      ; 3.383 ns                ;