tlc5510.tan.summary

来自「altera Quartus II TLC晶片控制 可控制暫存器」· SUMMARY 代码 · 共 67 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : -1.782 ns
From           : D[6]
To             : DATA[6]~reg0
From Clock     : 
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 12.345 ns
From           : DATA[2]~reg0
To             : DATA[2]
From Clock     : CLK
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 2.517 ns
From           : D[0]
To             : DATA[0]~reg0
From Clock     : 
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case Minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 8.813 ns
From           : sta_G_CurrentState
To             : ADCLK
From Clock     : CLK
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : sta_G_CurrentState
To             : sta_G_CurrentState
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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