tlc5510.fit.qmsg

altera Quartus II TLC晶片控制 可控制暫存器

{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "0.888 ns register register " "Info: Estimated most critical path is register to register delay of 0.888 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sta_G_CurrentState 1 REG LAB_X8_Y10 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X8_Y10; Fanout = 10; REG Node = 'sta_G_CurrentState'" {  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { sta_G_CurrentState } "NODE_NAME" } "" } } { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.150 ns) + CELL(0.738 ns) 0.888 ns sta_G_CurrentState 2 REG LAB_X8_Y10 10 " "Info: 2: + IC(0.150 ns) + CELL(0.738 ns) = 0.888 ns; Loc. = LAB_X8_Y10; Fanout = 10; REG Node = 'sta_G_CurrentState'" {  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "0.888 ns" { sta_G_CurrentState sta_G_CurrentState } "NODE_NAME" } "" } } { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.738 ns 83.11 % " "Info: Total cell delay = 0.738 ns ( 83.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.150 ns 16.89 % " "Info: Total interconnect delay = 0.150 ns ( 16.89 % )" {  } {  } 0}  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "0.888 ns" { sta_G_CurrentState sta_G_CurrentState } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: The following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ADOE GND " "Info: Pin ADOE has GND driving its datain port" {  } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 8 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "ADOE" } } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { ADOE } "NODE_NAME" } "" } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" "" { ADOE } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 25 22:22:16 2006 " "Info: Processing ended: Sun Jun 25 22:22:16 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0}  } {  } 0}