tlc5510.fit.qmsg

altera Quartus II TLC晶片控制 可控制暫存器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jun 25 22:22:09 2006 " "Info: Processing started: Sun Jun 25 22:22:09 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off TLC5510 -c TLC5510 " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off TLC5510 -c TLC5510" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "TLC5510 EP1C6F256C8 " "Info: Selected device EP1C6F256C8 for design \"TLC5510\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12F256C8 " "Info: Device EP1C12F256C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "19 19 " "Info: No exact pin location assignment(s) for 19 pins of 19 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "ADCLK " "Info: Pin ADCLK not assigned to an exact location on the device" {  } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 7 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "ADCLK" } } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { ADCLK } "NODE_NAME" } "" } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" "" { ADCLK } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "ADOE " "Info: Pin ADOE not assigned to an exact location on the device" {  } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 8 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "ADOE" } } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { ADOE } "NODE_NAME" } "" } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" "" { ADOE } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DATA\[0\] " "Info: Pin DATA\[0\] not assigned to an exact location on the device" {  } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 9 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DATA\[0\]" } } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { DATA[0] } "NODE_NAME" } "" } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" "" { DATA[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DATA\[1\] " "Info: Pin DATA\[1\] not assigned to an exact location on the device" {  } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 9 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DATA\[1\]" } } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { DATA[1] } "NODE_NAME" } "" } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" "" { DATA[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DATA\[2\] " "Info: Pin DATA\[2\] not assigned to an exact location on the device" {  } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 9 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DATA\[2\]" } } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { DATA[2] } "NODE_NAME" } "" } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" "" { DATA[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DATA\[3\] " "Info: Pin DATA\[3\] not assigned to an exact location on the device" {  } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 9 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DATA\[3\]" } } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { DATA[3] } "NODE_NAME" } "" } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" "" { DATA[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DATA\[4\] " "Info: Pin DATA\[4\] not assigned to an exact location on the device" {  } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 9 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DATA\[4\]" } } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { DATA[4] } "NODE_NAME" } "" } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" "" { DATA[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DATA\[5\] " "Info: Pin DATA\[5\] not assigned to an exact location on the device" {  } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 9 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DATA\[5\]" } } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { DATA[5] } "NODE_NAME" } "" } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" "" { DATA[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DATA\[6\] " "Info: Pin DATA\[6\] not assigned to an exact location on the device" {  } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 9 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DATA\[6\]" } } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { DATA[6] } "NODE_NAME" } "" } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" "" { DATA[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DATA\[7\] " "Info: Pin DATA\[7\] not assigned to an exact location on the device" {  } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 9 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DATA\[7\]" } } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { DATA[7] } "NODE_NAME" } "" } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" "" { DATA[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "CLK " "Info: Pin CLK not assigned to an exact location on the device" {  } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 5 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { CLK } "NODE_NAME" } "" } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" "" { CLK } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "D\[0\] " "Info: Pin D\[0\] not assigned to an exact location on the device" {  } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 6 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "D\[0\]" } } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { D[0] } "NODE_NAME" } "" } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" "" { D[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "D\[1\] " "Info: Pin D\[1\] not assigned to an exact location on the device" {  } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 6 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "D\[1\]" } } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { D[1] } "NODE_NAME" } "" } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" "" { D[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "D\[2\] " "Info: Pin D\[2\] not assigned to an exact location on the device" {  } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 6 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "D\[2\]" } } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { D[2] } "NODE_NAME" } "" } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" "" { D[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "D\[3\] " "Info: Pin D\[3\] not assigned to an exact location on the device" {  } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 6 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "D\[3\]" } } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { D[3] } "NODE_NAME" } "" } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" "" { D[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "D\[4\] " "Info: Pin D\[4\] not assigned to an exact location on the device" {  } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 6 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "D\[4\]" } } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { D[4] } "NODE_NAME" } "" } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" "" { D[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "D\[5\] " "Info: Pin D\[5\] not assigned to an exact location on the device" {  } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 6 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "D\[5\]" } } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { D[5] } "NODE_NAME" } "" } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" "" { D[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "D\[6\] " "Info: Pin D\[6\] not assigned to an exact location on the device" {  } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 6 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "D\[6\]" } } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { D[6] } "NODE_NAME" } "" } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" "" { D[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "D\[7\] " "Info: Pin D\[7\] not assigned to an exact location on the device" {  } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 6 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "D\[7\]" } } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { D[7] } "NODE_NAME" } "" } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.fld" "" "" { D[7] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sta_G_CurrentState Global clock " "Info: Automatically promoted some destinations of signal \"sta_G_CurrentState\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "ADCLK " "Info: Destination \"ADCLK\" may be non-global or may not use global clock" {  } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 7 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sta_G_CurrentState " "Info: Destination \"sta_G_CurrentState\" may be non-global or may not use global clock" {  } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 18 -1 0 } }  } 0}  } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 18 -1 0 } }  } 0}