tlc5510.map.qmsg

altera Quartus II TLC晶片控制 可控制暫存器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jun 25 22:22:04 2006 " "Info: Processing started: Sun Jun 25 22:22:04 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off TLC5510 -c TLC5510 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off TLC5510 -c TLC5510" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TLC5510.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file TLC5510.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 TLC5510-behavioural " "Info: Found design unit 1: TLC5510-behavioural" {  } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 14 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 TLC5510 " "Info: Found entity 1: TLC5510" {  } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "TLC5510 " "Info: Elaborating entity \"TLC5510\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "TLC5510.vhd(31) " "Info: VHDL Case Statement information at TLC5510.vhd(31): OTHERS choice is never selected" {  } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 31 0 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "ADOE GND " "Warning: Pin \"ADOE\" stuck at GND" {  } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 8 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "28 " "Info: Implemented 28 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "9 " "Info: Implemented 9 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "9 " "Info: Implemented 9 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 25 22:22:07 2006 " "Info: Processing ended: Sun Jun 25 22:22:07 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}