📄 tlc5510.fit.eqn
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
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-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--sta_G_CurrentState is sta_G_CurrentState at LC_X8_Y10_N6
--operation mode is normal
sta_G_CurrentState_lut_out = !sta_G_CurrentState;
sta_G_CurrentState = DFFEAS(sta_G_CurrentState_lut_out, CLK, VCC, , , , , , );
--A1L51Q is DATA[0]~reg0 at LC_X1_Y20_N2
--operation mode is normal
A1L51Q_lut_out = GND;
A1L51Q = DFFEAS(A1L51Q_lut_out, !GLOBAL(sta_G_CurrentState), VCC, , , D[0], , , VCC);
--A1L71Q is DATA[1]~reg0 at LC_X14_Y1_N2
--operation mode is normal
A1L71Q_lut_out = GND;
A1L71Q = DFFEAS(A1L71Q_lut_out, !GLOBAL(sta_G_CurrentState), VCC, , , D[1], , , VCC);
--A1L91Q is DATA[2]~reg0 at LC_X26_Y19_N2
--operation mode is normal
A1L91Q_lut_out = D[2];
A1L91Q = DFFEAS(A1L91Q_lut_out, !GLOBAL(sta_G_CurrentState), VCC, , , , , , );
--A1L12Q is DATA[3]~reg0 at LC_X6_Y1_N2
--operation mode is normal
A1L12Q_lut_out = GND;
A1L12Q = DFFEAS(A1L12Q_lut_out, !GLOBAL(sta_G_CurrentState), VCC, , , D[3], , , VCC);
--A1L32Q is DATA[4]~reg0 at LC_X2_Y1_N2
--operation mode is normal
A1L32Q_lut_out = GND;
A1L32Q = DFFEAS(A1L32Q_lut_out, !GLOBAL(sta_G_CurrentState), VCC, , , D[4], , , VCC);
--A1L52Q is DATA[5]~reg0 at LC_X4_Y1_N2
--operation mode is normal
A1L52Q_lut_out = D[5];
A1L52Q = DFFEAS(A1L52Q_lut_out, !GLOBAL(sta_G_CurrentState), VCC, , , , , , );
--A1L72Q is DATA[6]~reg0 at LC_X12_Y1_N2
--operation mode is normal
A1L72Q_lut_out = D[6];
A1L72Q = DFFEAS(A1L72Q_lut_out, !GLOBAL(sta_G_CurrentState), VCC, , , , , , );
--A1L92Q is DATA[7]~reg0 at LC_X8_Y20_N2
--operation mode is normal
A1L92Q_lut_out = D[7];
A1L92Q = DFFEAS(A1L92Q_lut_out, !GLOBAL(sta_G_CurrentState), VCC, , , , , , );
--CLK is CLK at PIN_J1
--operation mode is input
CLK = INPUT();
--D[0] is D[0] at PIN_D4
--operation mode is input
D[0] = INPUT();
--D[1] is D[1] at PIN_T8
--operation mode is input
D[1] = INPUT();
--D[2] is D[2] at PIN_B11
--operation mode is input
D[2] = INPUT();
--D[3] is D[3] at PIN_R5
--operation mode is input
D[3] = INPUT();
--D[4] is D[4] at PIN_T2
--operation mode is input
D[4] = INPUT();
--D[5] is D[5] at PIN_R4
--operation mode is input
D[5] = INPUT();
--D[6] is D[6] at PIN_R8
--operation mode is input
D[6] = INPUT();
--D[7] is D[7] at PIN_E6
--operation mode is input
D[7] = INPUT();
--ADCLK is ADCLK at PIN_M6
--operation mode is output
ADCLK = OUTPUT(!sta_G_CurrentState);
--ADOE is ADOE at PIN_E14
--operation mode is output
ADOE = OUTPUT(GND);
--DATA[0] is DATA[0] at PIN_C3
--operation mode is output
DATA[0] = OUTPUT(A1L51Q);
--DATA[1] is DATA[1] at PIN_N7
--operation mode is output
DATA[1] = OUTPUT(A1L71Q);
--DATA[2] is DATA[2] at PIN_D11
--operation mode is output
DATA[2] = OUTPUT(A1L91Q);
--DATA[3] is DATA[3] at PIN_P5
--operation mode is output
DATA[3] = OUTPUT(A1L12Q);
--DATA[4] is DATA[4] at PIN_R3
--operation mode is output
DATA[4] = OUTPUT(A1L32Q);
--DATA[5] is DATA[5] at PIN_P4
--operation mode is output
DATA[5] = OUTPUT(A1L52Q);
--DATA[6] is DATA[6] at PIN_T6
--operation mode is output
DATA[6] = OUTPUT(A1L72Q);
--DATA[7] is DATA[7] at PIN_D5
--operation mode is output
DATA[7] = OUTPUT(A1L92Q);
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