tlc5510.tan.rpt

altera Quartus II TLC晶片控制 可控制暫存器

; N/A   ; None         ; 8.813 ns   ; sta_G_CurrentState ; ADCLK   ; CLK        ;
+-------+--------------+------------+--------------------+---------+------------+


+--------------------------------------------------------------------------+
; th                                                                       ;
+---------------+-------------+-----------+------+--------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To           ; To Clock ;
+---------------+-------------+-----------+------+--------------+----------+
; N/A           ; None        ; 2.517 ns  ; D[0] ; DATA[0]~reg0 ; CLK      ;
; N/A           ; None        ; 2.009 ns  ; D[4] ; DATA[4]~reg0 ; CLK      ;
; N/A           ; None        ; 2.009 ns  ; D[3] ; DATA[3]~reg0 ; CLK      ;
; N/A           ; None        ; 2.009 ns  ; D[1] ; DATA[1]~reg0 ; CLK      ;
; N/A           ; None        ; 1.893 ns  ; D[2] ; DATA[2]~reg0 ; CLK      ;
; N/A           ; None        ; 1.885 ns  ; D[7] ; DATA[7]~reg0 ; CLK      ;
; N/A           ; None        ; 1.835 ns  ; D[5] ; DATA[5]~reg0 ; CLK      ;
; N/A           ; None        ; 1.834 ns  ; D[6] ; DATA[6]~reg0 ; CLK      ;
+---------------+-------------+-----------+------+--------------+----------+


+-----------------------------------------------------------------------------------------------+
; Minimum tco                                                                                   ;
+---------------+------------------+----------------+--------------------+---------+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From               ; To      ; From Clock ;
+---------------+------------------+----------------+--------------------+---------+------------+
; N/A           ; None             ; 8.813 ns       ; sta_G_CurrentState ; ADCLK   ; CLK        ;
; N/A           ; None             ; 12.149 ns      ; DATA[0]~reg0       ; DATA[0] ; CLK        ;
; N/A           ; None             ; 12.231 ns      ; DATA[3]~reg0       ; DATA[3] ; CLK        ;
; N/A           ; None             ; 12.233 ns      ; DATA[1]~reg0       ; DATA[1] ; CLK        ;
; N/A           ; None             ; 12.233 ns      ; DATA[4]~reg0       ; DATA[4] ; CLK        ;
; N/A           ; None             ; 12.233 ns      ; DATA[5]~reg0       ; DATA[5] ; CLK        ;
; N/A           ; None             ; 12.233 ns      ; DATA[6]~reg0       ; DATA[6] ; CLK        ;
; N/A           ; None             ; 12.286 ns      ; DATA[7]~reg0       ; DATA[7] ; CLK        ;
; N/A           ; None             ; 12.345 ns      ; DATA[2]~reg0       ; DATA[2] ; CLK        ;
+---------------+------------------+----------------+--------------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sun Jun 25 22:22:23 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off TLC5510 -c TLC5510 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "sta_G_CurrentState" as buffer
Info: Clock "CLK" Internal fmax is restricted to 275.03 MHz between source register "sta_G_CurrentState" and destination register "sta_G_CurrentState"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.823 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y10_N6; Fanout = 10; REG Node = 'sta_G_CurrentState'
            Info: 2: + IC(0.514 ns) + CELL(0.309 ns) = 0.823 ns; Loc. = LC_X8_Y10_N6; Fanout = 10; REG Node = 'sta_G_CurrentState'
            Info: Total cell delay = 0.309 ns ( 37.55 % )
            Info: Total interconnect delay = 0.514 ns ( 62.45 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK" to destination register is 4.172 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J1; Fanout = 1; CLK Node = 'CLK'
                Info: 2: + IC(1.992 ns) + CELL(0.711 ns) = 4.172 ns; Loc. = LC_X8_Y10_N6; Fanout = 10; REG Node = 'sta_G_CurrentState'
                Info: Total cell delay = 2.180 ns ( 52.25 % )
                Info: Total interconnect delay = 1.992 ns ( 47.75 % )
            Info: - Longest clock path from clock "CLK" to source register is 4.172 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J1; Fanout = 1; CLK Node = 'CLK'
                Info: 2: + IC(1.992 ns) + CELL(0.711 ns) = 4.172 ns; Loc. = LC_X8_Y10_N6; Fanout = 10; REG Node = 'sta_G_CurrentState'
                Info: Total cell delay = 2.180 ns ( 52.25 % )
                Info: Total interconnect delay = 1.992 ns ( 47.75 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "DATA[6]~reg0" (data pin = "D[6]", clock pin = "CLK") is -1.782 ns
    Info: + Longest pin to register delay is 6.788 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_R8; Fanout = 1; PIN Node = 'D[6]'
        Info: 2: + IC(5.004 ns) + CELL(0.309 ns) = 6.788 ns; Loc. = LC_X12_Y1_N2; Fanout = 1; REG Node = 'DATA[6]~reg0'
        Info: Total cell delay = 1.784 ns ( 26.28 % )
        Info: Total interconnect delay = 5.004 ns ( 73.72 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 8.607 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J1; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(1.992 ns) + CELL(0.935 ns) = 4.396 ns; Loc. = LC_X8_Y10_N6; Fanout = 10; REG Node = 'sta_G_CurrentState'
        Info: 3: + IC(3.500 ns) + CELL(0.711 ns) = 8.607 ns; Loc. = LC_X12_Y1_N2; Fanout = 1; REG Node = 'DATA[6]~reg0'
        Info: Total cell delay = 3.115 ns ( 36.19 % )
        Info: Total interconnect delay = 5.492 ns ( 63.81 % )
Info: tco from clock "CLK" to destination pin "DATA[2]" through register "DATA[2]~reg0" is 12.345 ns
    Info: + Longest clock path from clock "CLK" to source register is 8.666 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J1; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(1.992 ns) + CELL(0.935 ns) = 4.396 ns; Loc. = LC_X8_Y10_N6; Fanout = 10; REG Node = 'sta_G_CurrentState'
        Info: 3: + IC(3.559 ns) + CELL(0.711 ns) = 8.666 ns; Loc. = LC_X26_Y19_N2; Fanout = 1; REG Node = 'DATA[2]~reg0'
        Info: Total cell delay = 3.115 ns ( 35.95 % )
        Info: Total interconnect delay = 5.551 ns ( 64.05 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 3.455 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y19_N2; Fanout = 1; REG Node = 'DATA[2]~reg0'
        Info: 2: + IC(1.347 ns) + CELL(2.108 ns) = 3.455 ns; Loc. = PIN_D11; Fanout = 0; PIN Node = 'DATA[2]'
        Info: Total cell delay = 2.108 ns ( 61.01 % )
        Info: Total interconnect delay = 1.347 ns ( 38.99 % )
Info: th for register "DATA[0]~reg0" (data pin = "D[0]", clock pin = "CLK") is 2.517 ns
    Info: + Longest clock path from clock "CLK" to destination register is 8.657 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J1; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(1.992 ns) + CELL(0.935 ns) = 4.396 ns; Loc. = LC_X8_Y10_N6; Fanout = 10; REG Node = 'sta_G_CurrentState'
        Info: 3: + IC(3.550 ns) + CELL(0.711 ns) = 8.657 ns; Loc. = LC_X1_Y20_N2; Fanout = 1; REG Node = 'DATA[0]~reg0'
        Info: Total cell delay = 3.115 ns ( 35.98 % )
        Info: Total interconnect delay = 5.542 ns ( 64.02 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 6.155 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_D4; Fanout = 1; PIN Node = 'D[0]'
        Info: 2: + IC(4.571 ns) + CELL(0.115 ns) = 6.155 ns; Loc. = LC_X1_Y20_N2; Fanout = 1; REG Node = 'DATA[0]~reg0'
        Info: Total cell delay = 1.584 ns ( 25.74 % )
        Info: Total interconnect delay = 4.571 ns ( 74.26 % )
Info: Minimum tco from clock "CLK" to destination pin "ADCLK" through register "sta_G_CurrentState" is 8.813 ns
    Info: + Shortest clock path from clock "CLK" to source register is 4.172 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J1; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(1.992 ns) + CELL(0.711 ns) = 4.172 ns; Loc. = LC_X8_Y10_N6; Fanout = 10; REG Node = 'sta_G_CurrentState'
        Info: Total cell delay = 2.180 ns ( 52.25 % )
        Info: Total interconnect delay = 1.992 ns ( 47.75 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Shortest register to pin delay is 4.417 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y10_N6; Fanout = 10; REG Node = 'sta_G_CurrentState'
        Info: 2: + IC(2.309 ns) + CELL(2.108 ns) = 4.417 ns; Loc. = PIN_M6; Fanout = 0; PIN Node = 'ADCLK'
        Info: Total cell delay = 2.108 ns ( 47.72 % )
        Info: Total interconnect delay = 2.309 ns ( 52.28 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Sun Jun 25 22:22:23 2006
    Info: Elapsed time: 00:00:02