addvb_models_8.doc

VerilogHDL_advanced_digital_design_code_Ch8 VerilogHDL高级数字设计源码Ch8

vti_encoding:SR|utf8-nl
vti_timelastmodified:TR|30 Dec 2002 23:18:06 -0000
vti_extenderversion:SR|5.0.2.4330
vti_author:SR|EAS\\ciletti
vti_modifiedby:SR|EAS\\ciletti
vti_timecreated:TR|30 Dec 2002 23:18:06 -0000
vti_cacheddtm:TX|30 Dec 2002 23:18:06 -0000
vti_filesize:IR|107520
vti_cachedtitle:SR|IVC ‘95
vti_title:SR|IVC ‘95
vti_lineageid:SR|{C87DADC9-684A-4390-9BD7-712D18D453AB}
vti_backlinkinfo:VX|