📄 block1.fit.rpt
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; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ;
; Optimize Timing ; Normal compilation ; Normal compilation ;
; Optimize IOC Register Placement for Timing ; On ; On ;
; Limit to One Fitting Attempt ; Off ; Off ;
; Final Placement Optimizations ; Automatically ; Automatically ;
; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; Slow Slew Rate ; Off ; Off ;
; PCI I/O ; Off ; Off ;
; Weak Pull-Up Resistor ; Off ; Off ;
; Enable Bus-Hold Circuitry ; Off ; Off ;
; Auto Global Memory Control Signals ; Off ; Off ;
; Auto Packed Registers -- Cyclone ; Auto ; Auto ;
; Auto Delay Chains ; On ; On ;
; Auto Merge PLLs ; On ; On ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
; Perform Register Duplication for Performance ; Off ; Off ;
; Perform Register Retiming for Performance ; Off ; Off ;
; Perform Asynchronous Signal Pipelining ; Off ; Off ;
; Fitter Effort ; Auto Fit ; Auto Fit ;
; Physical Synthesis Effort Level ; Normal ; Normal ;
; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
; Auto Register Duplication ; Auto ; Auto ;
; Auto Global Clock ; On ; On ;
; Auto Global Register Control Signals ; On ; On ;
; Stop After Congestion Map Generation ; Off ; Off ;
; Save Intermediate Fitting Results ; Off ; Off ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in C:/Documents and Settings/Administrator/桌面/yue/Block1.pin.
+-----------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary ;
+---------------------------------------------+-------------------------------------------------------------------------+
; Resource ; Usage ;
+---------------------------------------------+-------------------------------------------------------------------------+
; Total logic elements ; 291 / 2,910 ( 10 % ) ;
; -- Combinational with no register ; 140 ;
; -- Register only ; 18 ;
; -- Combinational with a register ; 133 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 97 ;
; -- 3 input functions ; 49 ;
; -- 2 input functions ; 114 ;
; -- 1 input functions ; 20 ;
; -- 0 input functions ; 11 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 235 ;
; -- arithmetic mode ; 56 ;
; -- qfbk mode ; 2 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 52 ;
; -- asynchronous clear/load mode ; 63 ;
; ; ;
; Total registers ; 151 / 3,210 ( 5 % ) ;
; Total LABs ; 44 / 291 ( 15 % ) ;
; Logic elements in carry chains ; 63 ;
; User inserted logic elements ; 0 ;
; Virtual pins ; 0 ;
; I/O pins ; 6 / 104 ( 6 % ) ;
; -- Clock pins ; 1 / 2 ( 50 % ) ;
; Global signals ; 8 ;
; M4Ks ; 1 / 13 ( 8 % ) ;
; Total memory bits ; 1,024 / 59,904 ( 2 % ) ;
; Total RAM block bits ; 4,608 / 59,904 ( 8 % ) ;
; PLLs ; 1 / 1 ( 100 % ) ;
; Global clocks ; 8 / 8 ( 100 % ) ;
; Average interconnect usage ; 2% ;
; Peak interconnect usage ; 3% ;
; Maximum fan-out node ; altera_internal_jtag~TDO ;
; Maximum fan-out ; 107 ;
; Highest non-global fan-out signal ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] ;
; Highest non-global fan-out ; 33 ;
; Total fan-out ; 1115 ;
; Average fan-out ; 3.69 ;
+---------------------------------------------+-------------------------------------------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; inclk ; 16 ; 1 ; 0 ; 8 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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