clock2.vhd

来自「vhdl实现音乐播放,播放梁祝乐曲」· VHDL 代码 · 共 24 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clock2 is
  port(clkin:in std_logic;     
       clkout:buffer std_logic  
       );
end entity;

architecture arc of clock2 is
begin
 process(clkin) 
  begin
    if (clkin'event and clkin='1') then
    	clkout <= not clkout;
    end if;
  end process;
end arc;