block1.tan.qmsg

vhdl实现音乐播放,播放梁祝乐曲

{ "Warning" "WTAN_FULL_MINIMUM_REQUIREMENTS_NOT_MET" "kkk:inst\|altpll:altpll_component\|_clk0 42 " "Warning: Can't achieve minimum setup and hold requirement kkk:inst\|altpll:altpll_component\|_clk0 along 42 path(s). See Report window for details." {  } {  } 0 0 "Can't achieve minimum setup and hold requirement %1!s! along %2!d! path(s). See Report window for details." 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "sld_hub:sld_hub_inst\|jtag_debug_mode altera_internal_jtag~TMSUTAP altera_internal_jtag~TCKUTAP -0.130 ns register " "Info: tsu for register \"sld_hub:sld_hub_inst\|jtag_debug_mode\" (data pin = \"altera_internal_jtag~TMSUTAP\", clock pin = \"altera_internal_jtag~TCKUTAP\") is -0.130 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.109 ns + Longest pin register " "Info: + Longest pin to register delay is 5.109 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TMSUTAP 1 PIN JTAG_X1_Y6_N1 23 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 23; PIN Node = 'altera_internal_jtag~TMSUTAP'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera