📄 prev_cmp_block1.tan.qmsg
字号:
{ "Info" "ITAN_NO_REG2REG_EXIST" "inclk " "Info: No valid register-to-register data paths exist for clock \"inclk\"" { } { } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|HUB_BYPASS_REG register sld_hub:sld_hub_inst\|hub_tdo_reg 67.12 MHz 14.898 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 67.12 MHz between source register \"sld_hub:sld_hub_inst\|HUB_BYPASS_REG\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo_reg\" (period= 14.898 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.226 ns + Longest register register " "Info: + Longest register to register delay is 7.226 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|HUB_BYPASS_REG 1 REG LC_X19_Y5_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y5_N5; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|HUB_BYPASS_REG'" { } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|HUB_BYPASS_REG } "NODE_NAME" } } { "c:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/quartus/libraries/megafunctions/sld_hub.vhd" 325 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.028 ns) + CELL(0.590 ns) 2.618 ns sld_hub:sld_hub_inst\|hub_tdo_reg~292 2 COMB LC_X12_Y7_N4 1 " "Info: 2: + IC(2.028 ns) + CELL(0.590 ns) = 2.618 ns; Loc. = LC_X12_Y7_N4; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~292'" { } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "2.618 ns" { sld_hub:sld_hub_inst|HUB_BYPASS_REG sld_hub:sld_hub_inst|hub_tdo_reg~292 } "NODE_NAME" } } { "c:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.002 ns) + CELL(0.590 ns) 5.210 ns sld_hub:sld_hub_inst\|hub_tdo_reg~293 3 COMB LC_X17_Y8_N2 1 " "Info: 3: + IC(2.002 ns) + CELL(0.590 ns) = 5.210 ns; Loc. = LC_X17_Y8_N2; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~293'" { } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "2.592 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~292 sld_hub:sld_hub_inst|hub_tdo_reg~293 } "NODE_NAME" } } { "c:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.538 ns) + CELL(0.478 ns) 7.226 ns sld_hub:sld_hub_inst\|hub_tdo_reg 4 REG LC_X19_Y6_N3 2 " "Info: 4: + IC(1.538 ns) + CELL(0.478 ns) = 7.226 ns; Loc. = LC_X19_Y6_N3; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" { } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "2.016 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~293 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.658 ns ( 22.94 % ) " "Info: Total cell delay = 1.658 ns ( 22.94 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.568 ns ( 77.06 % ) " "Info: Total interconnect delay = 5.568 ns ( 77.06 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "7.226 ns" { sld_hub:sld_hub_inst|HUB_BYPASS_REG sld_hub:sld_hub_inst|hub_tdo_reg~292 sld_hub:sld_hub_inst|hub_tdo_reg~293 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/bin/Technology_Viewer.qrui" "7.226 ns" { sld_hub:sld_hub_inst|HUB_BYPASS_REG {} sld_hub:sld_hub_inst|hub_tdo_reg~292 {} sld_hub:sld_hub_inst|hub_tdo_reg~293 {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 2.028ns 2.002ns 1.538ns } { 0.000ns 0.590ns 0.590ns 0.478ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.038 ns - Smallest " "Info: - Smallest clock skew is 0.038 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.272 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.272 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 117 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 117; CLK Node = 'altera_internal_jtag~TCKUTAP'" { } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.561 ns) + CELL(0.711 ns) 5.272 ns sld_hub:sld_hub_inst\|hub_tdo_reg 2 REG LC_X19_Y6_N3 2 " "Info: 2: + IC(4.561 ns) + CELL(0.711 ns) = 5.272 ns; Loc. = LC_X19_Y6_N3; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" { } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.49 % ) " "Info: Total cell delay = 0.711 ns ( 13.49 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.561 ns ( 86.51 % ) " "Info: Total interconnect delay = 4.561 ns ( 86.51 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/bin/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 4.561ns } { 0.000ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.234 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.234 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 117 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 117; CLK Node = 'altera_internal_jtag~TCKUTAP'" { } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.523 ns) + CELL(0.711 ns) 5.234 ns sld_hub:sld_hub_inst\|HUB_BYPASS_REG 2 REG LC_X19_Y5_N5 1 " "Info: 2: + IC(4.523 ns) + CELL(0.711 ns) = 5.234 ns; Loc. = LC_X19_Y5_N5; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|HUB_BYPASS_REG'" { } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "5.234 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_BYPASS_REG } "NODE_NAME" } } { "c:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/quartus/libraries/megafunctions/sld_hub.vhd" 325 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.58 % ) " "Info: Total cell delay = 0.711 ns ( 13.58 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.523 ns ( 86.42 % ) " "Info: Total interconnect delay = 4.523 ns ( 86.42 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "5.234 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_BYPASS_REG } "NODE_NAME" } } { "c:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/bin/Technology_Viewer.qrui" "5.234 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|HUB_BYPASS_REG {} } { 0.000ns 4.523ns } { 0.000ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/bin/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 4.561ns } { 0.000ns 0.711ns } "" } } { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "5.234 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_BYPASS_REG } "NODE_NAME" } } { "c:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/bin/Technology_Viewer.qrui" "5.234 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|HUB_BYPASS_REG {} } { 0.000ns 4.523ns } { 0.000ns 0.711ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "c:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/quartus/libraries/megafunctions/sld_hub.vhd" 325 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "c:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" { } { { "c:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/quartus/libraries/megafunctions/sld_hub.vhd" 325 -1 0 } } { "c:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0} } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "7.226 ns" { sld_hub:sld_hub_inst|HUB_BYPASS_REG sld_hub:sld_hub_inst|hub_tdo_reg~292 sld_hub:sld_hub_inst|hub_tdo_reg~293 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/bin/Technology_Viewer.qrui" "7.226 ns" { sld_hub:sld_hub_inst|HUB_BYPASS_REG {} sld_hub:sld_hub_inst|hub_tdo_reg~292 {} sld_hub:sld_hub_inst|hub_tdo_reg~293 {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 2.028ns 2.002ns 1.538ns } { 0.000ns 0.590ns 0.590ns 0.478ns } "" } } { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/bin/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 4.561ns } { 0.000ns 0.711ns } "" } } { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "5.234 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_BYPASS_REG } "NODE_NAME" } } { "c:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/bin/Technology_Viewer.qrui" "5.234 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|HUB_BYPASS_REG {} } { 0.000ns 4.523ns } { 0.000ns 0.711ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "kkk:inst\|altpll:altpll_component\|_clk0 memory notetabs:inst4\|music_rom:u1\|altsyncram:altsyncram_component\|altsyncram_gq41:auto_generated\|altsyncram_8962:altsyncram1\|q_a\[2\] register ToneTaba:inst6\|Tone\[10\] -4.124 ns " "Info: Minimum slack time is -4.124 ns for clock \"kkk:inst\|altpll:altpll_component\|_clk0\" between source memory \"notetabs:inst4\|music_rom:u1\|altsyncram:altsyncram_component\|altsyncram_gq41:auto_generated\|altsyncram_8962:altsyncram1\|q_a\[2\]\" and destination register \"ToneTaba:inst6\|Tone\[10\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.948 ns + Shortest memory register " "Info: + Shortest memory to register delay is 2.948 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.104 ns) 0.104 ns notetabs:inst4\|music_rom:u1\|altsyncram:altsyncram_component\|altsyncram_gq41:auto_generated\|altsyncram_8962:altsyncram1\|q_a\[2\] 1 MEM M4K_X13_Y6 11 " "Info: 1: + IC(0.000 ns) + CELL(0.104 ns) = 0.104 ns; Loc. = M4K_X13_Y6; Fanout = 11; MEM Node = 'notetabs:inst4\|music_rom:u1\|altsyncram:altsyncram_component\|altsyncram_gq41:auto_generated\|altsyncram_8962:altsyncram1\|q_a\[2\]'" { } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "" { notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|altsyncram_8962:altsyncram1|q_a[2] } "NODE_NAME" } } { "db/altsyncram_8962.tdf" "" { Text "D:/Documents and Settings/yyy/桌面/yue/db/altsyncram_8962.tdf" 34 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.715 ns) + CELL(0.114 ns) 1.933 ns ToneTaba:inst6\|Mux17~33 2 COMB LC_X23_Y6_N2 1 " "Info: 2: + IC(1.715 ns) + CELL(0.114 ns) = 1.933 ns; Loc. = LC_X23_Y6_N2; Fanout = 1; COMB Node = 'ToneTaba:inst6\|Mux17~33'" { } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "1.829 ns" { notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|altsyncram_8962:altsyncram1|q_a[2] ToneTaba:inst6|Mux17~33 } "NODE_NAME" } } { "ToneTaba.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/ToneTaba.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.425 ns) + CELL(0.590 ns) 2.948 ns ToneTaba:inst6\|Tone\[10\] 3 REG LC_X23_Y6_N5 1 " "Info: 3: + IC(0.425 ns) + CELL(0.590 ns) = 2.948 ns; Loc. = LC_X23_Y6_N5; Fanout = 1; REG Node = 'ToneTaba:inst6\|Tone\[10\]'" { } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "1.015 ns" { ToneTaba:inst6|Mux17~33 ToneTaba:inst6|Tone[10] } "NODE_NAME" } } { "ToneTaba.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/ToneTaba.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.808 ns ( 27.41 % ) " "Info: Total cell delay = 0.808 ns ( 27.41 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.140 ns ( 72.59 % ) " "Info: Total interconnect delay = 2.140 ns ( 72.59 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "2.948 ns" { notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|altsyncram_8962:altsyncram1|q_a[2] ToneTaba:inst6|Mux17~33 ToneTaba:inst6|Tone[10] } "NODE_NAME" } } { "c:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/bin/Technology_Viewer.qrui" "2.948 ns" { notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|altsyncram_8962:altsyncram1|q_a[2] {} ToneTaba:inst6|Mux17~33 {} ToneTaba:inst6|Tone[10] {} } { 0.000ns 1.715ns 0.425ns } { 0.104ns 0.114ns 0.590ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "7.072 ns - Smallest memory register " "Info: - Smallest memory to register requirement is 7.072 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -1.833 ns " "Info: + Latch edge is -1.833 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination kkk:inst\|altpll:altpll_component\|_clk0 41.666 ns -1.833 ns 50 " "Info: Clock period of Destination clock \"kkk:inst\|altpll:altpll_component\|_clk0\" is 41.666 ns with offset of -1.833 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.833 ns " "Info: - Launch edge is -1.833 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source kkk:inst\|altpll:altpll_component\|_clk0 41.666 ns -1.833 ns 50 " "Info: Clock period of Source clock \"kkk:inst\|altpll:altpll_component\|_clk0\" is 41.666 ns with offset of -1.833 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "7.722 ns + Smallest " "Info: + Smallest clock skew is 7.722 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "kkk:inst\|altpll:altpll_component\|_clk0 destination 15.712 ns + Longest register " "Info: + Longest clock path from clock \"kkk:inst\|altpll:altpll_component\|_clk0\" to destination register is 15.712 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns kkk:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_1 24 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 24; CLK Node = 'kkk:inst\|altpll:altpll_component\|_clk0'" { } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "" { kkk:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.611 ns) + CELL(0.935 ns) 2.546 ns clock3000000:inst3\|clkout 2 REG LC_X15_Y6_N8 29 " "Info: 2: + IC(1.611 ns) + CELL(0.935 ns) = 2.546 ns; Loc. = LC_X15_Y6_N8; Fanout = 29; REG Node = 'clock3000000:inst3\|clkout'" { } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "2.546 ns" { kkk:inst|altpll:altpll_component|_clk0 clock3000000:inst3|clkout } "NODE_NAME" } } { "clock3000000.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/clock3000000.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.736 ns) + CELL(1.462 ns) 8.744 ns notetabs:inst4\|music_rom:u1\|altsyncram:altsyncram_component\|altsyncram_gq41:auto_generated\|altsyncram_8962:altsyncram1\|q_a\[0\] 3 MEM M4K_X13_Y6 11 " "Info: 3: + IC(4.736 ns) + CELL(1.462 ns) = 8.744 ns; Loc. = M4K_X13_Y6; Fanout = 11; MEM Node = 'notetabs:inst4\|music_rom:u1\|altsyncram:altsyncram_component\|altsyncram_gq41:auto_generated\|altsyncram_8962:altsyncram1\|q_a\[0\]'" { } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "6.198 ns" { clock3000000:inst3|clkout notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|altsyncram_8962:altsyncram1|q_a[0] } "NODE_NAME" } } { "db/altsyncram_8962.tdf" "" { Text "D:/Documents and Settings/yyy/桌面/yue/db/altsyncram_8962.tdf" 34 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.971 ns) + CELL(0.442 ns) 11.157 ns ToneTaba:inst6\|Mux4~31 4 COMB LC_X26_Y6_N4 11 " "Info: 4: + IC(1.971 ns) + CELL(0.442 ns) = 11.157 ns; Loc. = LC_X26_Y6_N4; Fanout = 11; COMB Node = 'ToneTaba:inst6\|Mux4~31'" { } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "2.413 ns" { notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|altsyncram_8962:altsyncram1|q_a[0] ToneTaba:inst6|Mux4~31 } "NODE_NAME" } } { "ToneTaba.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/ToneTaba.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.263 ns) + CELL(0.292 ns) 15.712 ns ToneTaba:inst6\|Tone\[10\] 5 REG LC_X23_Y6_N5 1 " "Info: 5: + IC(4.263 ns) + CELL(0.292 ns) = 15.712 ns; Loc. = LC_X23_Y6_N5; Fanout = 1; REG Node = 'ToneTaba:inst6\|Tone\[10\]'" { } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "4.555 ns" { ToneTaba:inst6|Mux4~31 ToneTaba:inst6|Tone[10] } "NODE_NAME" } } { "ToneTaba.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/ToneTaba.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.131 ns ( 19.93 % ) " "Info: Total cell delay = 3.131 ns ( 19.93 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.581 ns ( 80.07 % ) " "Info: Total interconnect delay = 12.581 ns ( 80.07 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "15.712 ns" { kkk:inst|altpll:altpll_component|_clk0 clock3000000:inst3|clkout notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|altsyncram_8962:altsyncram1|q_a[0] ToneTaba:inst6|Mux4~31 ToneTaba:inst6|Tone[10] } "NODE_NAME" } } { "c:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/bin/Technology_Viewer.qrui" "15.712 ns" { kkk:inst|altpll:altpll_component|_clk0 {} clock3000000:inst3|clkout {} notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|altsyncram_8962:altsyncram1|q_a[0] {} ToneTaba:inst6|Mux4~31 {} ToneTaba:inst6|Tone[10] {} } { 0.000ns 1.611ns 4.736ns 1.971ns 4.263ns } { 0.000ns 0.935ns 1.462ns 0.442ns 0.292ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "kkk:inst\|altpll:altpll_component\|_clk0 source 7.990 ns - Shortest memory " "Info: - Shortest clock path from clock \"kkk:inst\|altpll:altpll_component\|_clk0\" to source memory is 7.990 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns kkk:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_1 24 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 24; CLK Node = 'kkk:inst\|altpll:altpll_component\|_clk0'" { } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "" { kkk:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.611 ns) + CELL(0.935 ns) 2.546 ns clock3000000:inst3\|clkout 2 REG LC_X15_Y6_N8 29 " "Info: 2: + IC(1.611 ns) + CELL(0.935 ns) = 2.546 ns; Loc. = LC_X15_Y6_N8; Fanout = 29; REG Node = 'clock3000000:inst3\|clkout'" { } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "2.546 ns" { kkk:inst|altpll:altpll_component|_clk0 clock3000000:inst3|clkout } "NODE_NAME" } } { "clock3000000.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/clock3000000.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.736 ns) + CELL(0.708 ns) 7.990 ns notetabs:inst4\|music_rom:u1\|altsyncram:altsyncram_component\|altsyncram_gq41:auto_generated\|altsyncram_8962:altsyncram1\|q_a\[2\] 3 MEM M4K_X13_Y6 11 " "Info: 3: + IC(4.736 ns) + CELL(0.708 ns) = 7.990 ns; Loc. = M4K_X13_Y6; Fanout = 11; MEM Node = 'notetabs:inst4\|music_rom:u1\|altsyncram:altsyncram_component\|altsyncram_gq41:auto_generated\|altsyncram_8962:altsyncram1\|q_a\[2\]'" { } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "5.444 ns" { clock3000000:inst3|clkout notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|altsyncram_8962:altsyncram1|q_a[2] } "NODE_NAME" } } { "db/altsyncram_8962.tdf" "" { Text "D:/Documents and Settings/yyy/桌面/yue/db/altsyncram_8962.tdf" 34 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.643 ns ( 20.56 % ) " "Info: Total cell delay = 1.643 ns ( 20.56 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.347 ns ( 79.44 % ) " "Info: Total interconnect delay = 6.347 ns ( 79.44 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "7.990 ns" { kkk:inst|altpll:altpll_component|_clk0 clock3000000:inst3|clkout notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|altsyncram_8962:altsyncram1|q_a[2] } "NODE_NAME" } } { "c:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/bin/Technology_Viewer.qrui" "7.990 ns" { kkk:inst|altpll:altpll_component|_clk0 {} clock3000000:inst3|clkout {} notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|altsyncram_8962:altsyncram1|q_a[2] {} } { 0.000ns 1.611ns 4.736ns } { 0.000ns 0.935ns 0.708ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "15.712 ns" { kkk:inst|altpll:altpll_component|_clk0 clock3000000:inst3|clkout notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|altsyncram_8962:altsyncram1|q_a[0] ToneTaba:inst6|Mux4~31 ToneTaba:inst6|Tone[10] } "NODE_NAME" } } { "c:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/bin/Technology_Viewer.qrui" "15.712 ns" { kkk:inst|altpll:altpll_component|_clk0 {} clock3000000:inst3|clkout {} notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|altsyncram_8962:altsyncram1|q_a[0] {} ToneTaba:inst6|Mux4~31 {} ToneTaba:inst6|Tone[10] {} } { 0.000ns 1.611ns 4.736ns 1.971ns 4.263ns } { 0.000ns 0.935ns 1.462ns 0.442ns 0.292ns } "" } } { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "7.990 ns" { kkk:inst|altpll:altpll_component|_clk0 clock3000000:inst3|clkout notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|altsyncram_8962:altsyncram1|q_a[2] } "NODE_NAME" } } { "c:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/bin/Technology_Viewer.qrui" "7.990 ns" { kkk:inst|altpll:altpll_component|_clk0 {} clock3000000:inst3|clkout {} notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|altsyncram_8962:altsyncram1|q_a[2] {} } { 0.000ns 1.611ns 4.736ns } { 0.000ns 0.935ns 0.708ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns - " "Info: - Micro clock to output delay of source is 0.650 ns" { } { { "db/altsyncram_8962.tdf" "" { Text "D:/Documents and Settings/yyy/桌面/yue/db/altsyncram_8962.tdf" 34 2 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" { } { { "ToneTaba.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/ToneTaba.vhd" 11 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "15.712 ns" { kkk:inst|altpll:altpll_component|_clk0 clock3000000:inst3|clkout notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|altsyncram_8962:altsyncram1|q_a[0] ToneTaba:inst6|Mux4~31 ToneTaba:inst6|Tone[10] } "NODE_NAME" } } { "c:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/bin/Technology_Viewer.qrui" "15.712 ns" { kkk:inst|altpll:altpll_component|_clk0 {} clock3000000:inst3|clkout {} notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|altsyncram_8962:altsyncram1|q_a[0] {} ToneTaba:inst6|Mux4~31 {} ToneTaba:inst6|Tone[10] {} } { 0.000ns 1.611ns 4.736ns 1.971ns 4.263ns } { 0.000ns 0.935ns 1.462ns 0.442ns 0.292ns } "" } } { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "7.990 ns" { kkk:inst|altpll:altpll_component|_clk0 clock3000000:inst3|clkout notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|altsyncram_8962:altsyncram1|q_a[2] } "NODE_NAME" } } { "c:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/bin/Technology_Viewer.qrui" "7.990 ns" { kkk:inst|altpll:altpll_component|_clk0 {} clock3000000:inst3|clkout {} notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|altsyncram_8962:altsyncram1|q_a[2] {} } { 0.000ns 1.611ns 4.736ns } { 0.000ns 0.935ns 0.708ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "2.948 ns" { notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|altsyncram_8962:altsyncram1|q_a[2] ToneTaba:inst6|Mux17~33 ToneTaba:inst6|Tone[10] } "NODE_NAME" } } { "c:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/bin/Technology_Viewer.qrui" "2.948 ns" { notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|altsyncram_8962:altsyncram1|q_a[2] {} ToneTaba:inst6|Mux17~33 {} ToneTaba:inst6|Tone[10] {} } { 0.000ns 1.715ns 0.425ns } { 0.104ns 0.114ns 0.590ns } "" } } { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "15.712 ns" { kkk:inst|altpll:altpll_component|_clk0 clock3000000:inst3|clkout notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|altsyncram_8962:altsyncram1|q_a[0] ToneTaba:inst6|Mux4~31 ToneTaba:inst6|Tone[10] } "NODE_NAME" } } { "c:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/bin/Technology_Viewer.qrui" "15.712 ns" { kkk:inst|altpll:altpll_component|_clk0 {} clock3000000:inst3|clkout {} notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|altsyncram_8962:altsyncram1|q_a[0] {} ToneTaba:inst6|Mux4~31 {} ToneTaba:inst6|Tone[10] {} } { 0.000ns 1.611ns 4.736ns 1.971ns 4.263ns } { 0.000ns 0.935ns 1.462ns 0.442ns 0.292ns } "" } } { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "7.990 ns" { kkk:inst|altpll:altpll_component|_clk0 clock3000000:inst3|clkout notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|altsyncram_8962:altsyncram1|q_a[2] } "NODE_NAME" } } { "c:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/bin/Technology_Viewer.qrui" "7.990 ns" { kkk:inst|altpll:altpll_component|_clk0 {} clock3000000:inst3|clkout {} notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|altsyncram_8962:altsyncram1|q_a[2] {} } { 0.000ns 1.611ns 4.736ns } { 0.000ns 0.935ns 0.708ns } "" } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -