prev_cmp_block1.tan.qmsg

vhdl实现音乐播放,播放梁祝乐曲

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "9 " "Warning: Found 9 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "ToneTaba:inst6\|Mux4~31 " "Info: Detected gated clock \"ToneTaba:inst6\|Mux4~31\" as buffer" {  } { { "ToneTaba.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/ToneTaba.vhd" 13 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "ToneTaba:inst6\|Mux4~31" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "Speakera:inst5\|FullSpkS " "Info: Detected ripple clock \"Speakera:inst5\|FullSpkS\" as buffer" {  } { { "Speakera.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/Speakera.vhd" 10 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "Speakera:inst5\|FullSpkS" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clock2:inst2\|clkout " "Info: Detected ripple clock \"clock2:inst2\|clkout\" as buffer" {  } { { "clock2.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/clock2.vhd" 11 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clock2:inst2\|clkout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "Speakera:inst5\|PreCLK " "Info: Detected ripple clock \"Speakera:inst5\|PreCLK\" as buffer" {  } { { "Speakera.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/Speakera.vhd" 10 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "Speakera:inst5\|PreCLK" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clock3000000:inst3\|clkout " "Info: Detected ripple clock \"clock3000000:inst3\|clkout\" as buffer" {  } { { "clock3000000.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/clock3000000.vhd" 7 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clock3000000:inst3\|clkout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "notetabs:inst4\|music_rom:u1\|altsyncram:altsyncram_component\|altsyncram_gq41:auto_generated\|altsyncram_8962:altsyncram1\|q_a\[1\] " "Info: Detected ripple clock \"notetabs:inst4\|music_rom:u1\|altsyncram:altsyncram_component\|altsyncram_gq41:auto_generated\|altsyncram_8962:altsyncram1\|q_a\[1\]\" as buffer" {  } { { "db/altsyncram_8962.tdf" "" { Text "D:/Documents and Settings/yyy/桌面/yue/db/altsyncram_8962.tdf" 34 2 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "notetabs:inst4\|music_rom:u1\|altsyncram:altsyncram_component\|altsyncram_gq41:auto_generated\|altsyncram_8962:altsyncram1\|q_a\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "notetabs:inst4\|music_rom:u1\|altsyncram:altsyncram_component\|altsyncram_gq41:auto_generated\|altsyncram_8962:altsyncram1\|q_a\[2\] " "Info: Detected ripple clock \"notetabs:inst4\|music_rom:u1\|altsyncram:altsyncram_component\|altsyncram_gq41:auto_generated\|altsyncram_8962:altsyncram1\|q_a\[2\]\" as buffer" {  } { { "db/altsyncram_8962.tdf" "" { Text "D:/Documents and Settings/yyy/桌面/yue/db/altsyncram_8962.tdf" 34 2 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "notetabs:inst4\|music_rom:u1\|altsyncram:altsyncram_component\|altsyncram_gq41:auto_generated\|altsyncram_8962:altsyncram1\|q_a\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "notetabs:inst4\|music_rom:u1\|altsyncram:altsyncram_component\|altsyncram_gq41:auto_generated\|altsyncram_8962:altsyncram1\|q_a\[3\] " "Info: Detected ripple clock \"notetabs:inst4\|music_rom:u1\|altsyncram:altsyncram_component\|altsyncram_gq41:auto_generated\|altsyncram_8962:altsyncram1\|q_a\[3\]\" as buffer" {  } { { "db/altsyncram_8962.tdf" "" { Text "D:/Documents and Settings/yyy/桌面/yue/db/altsyncram_8962.tdf" 34 2 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "notetabs:inst4\|music_rom:u1\|altsyncram:altsyncram_component\|altsyncram_gq41:auto_generated\|altsyncram_8962:altsyncram1\|q_a\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "notetabs:inst4\|music_rom:u1\|altsyncram:altsyncram_component\|altsyncram_gq41:auto_generated\|altsyncram_8962:altsyncram1\|q_a\[0\] " "Info: Detected ripple clock \"notetabs:inst4\|music_rom:u1\|altsyncram:altsyncram_component\|altsyncram_gq41:auto_generated\|altsyncram_8962:altsyncram1\|q_a\[0\]\" as buffer" {  } { { "db/altsyncram_8962.tdf" "" { Text "D:/Documents and Settings/yyy/桌面/yue/db/altsyncram_8962.tdf" 34 2 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "notetabs:inst4\|music_rom:u1\|altsyncram:altsyncram_component\|altsyncram_gq41:auto_generated\|altsyncram_8962:altsyncram1\|q_a\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0 "" 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "kkk:inst\|altpll:altpll_component\|_clk0 register clock3000000:inst3\|count\[5\] register clock3000000:inst3\|clkout 34.262 ns " "Info: Slack time is 34.262 ns for clock \"kkk:inst\|altpll:altpll_component\|_clk0\" between source register \"clock3000000:inst3\|count\[5\]\" and destination register \"clock3000000:inst3\|clkout\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "135.06 MHz 7.404 ns " "Info: Fmax is 135.06 MHz (period= 7.404 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "41.448 ns + Largest register register " "Info: + Largest register to register requirement is 41.448 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "41.666 ns + " "Info: + Setup relationship between source and destination is 41.666 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 39.833 ns " "Info: + Latch edge is 39.833 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination kkk:inst\|altpll:altpll_component\|_clk0 41.666 ns -1.833 ns  50 " "Info: Clock period of Destination clock \"kkk:inst\|altpll:altpll_component\|_clk0\" is 41.666 ns with  offset of -1.833 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.833 ns " "Info: - Launch edge is -1.833 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source kkk:inst\|altpll:altpll_component\|_clk0 41.666 ns -1.833 ns  50 " "Info: Clock period of Source clock \"kkk:inst\|altpll:altpll_component\|_clk0\" is 41.666 ns with  offset of -1.833 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.043 ns + Largest " "Info: + Largest clock skew is 0.043 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "kkk:inst\|altpll:altpll_component\|_clk0 destination 2.322 ns + Shortest register " "Info: + Shortest clock path from clock \"kkk:inst\|altpll:altpll_component\|_clk0\" to destination register is 2.322 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns kkk:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_1 24 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 24; CLK Node = 'kkk:inst\|altpll:altpll_component\|_clk0'" {  } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "" { kkk:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.611 ns) + CELL(0.711 ns) 2.322 ns clock3000000:inst3\|clkout 2 REG LC_X15_Y6_N8 29 " "Info: 2: + IC(1.611 ns) + CELL(0.711 ns) = 2.322 ns; Loc. = LC_X15_Y6_N8; Fanout = 29; REG Node = 'clock3000000:inst3\|clkout'" {  } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "2.322 ns" { kkk:inst|altpll:altpll_component|_clk0 clock3000000:inst3|clkout } "NODE_NAME" } } { "clock3000000.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/clock3000000.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 30.62 % ) " "Info: Total cell delay = 0.711 ns ( 30.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.611 ns ( 69.38 % ) " "Info: Total interconnect delay = 1.611 ns ( 69.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "2.322 ns" { kkk:inst|altpll:altpll_component|_clk0 clock3000000:inst3|clkout } "NODE_NAME" } } { "c:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/bin/Technology_Viewer.qrui" "2.322 ns" { kkk:inst|altpll:altpll_component|_clk0 {} clock3000000:inst3|clkout {} } { 0.000ns 1.611ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "kkk:inst\|altpll:altpll_component\|_clk0 source 2.279 ns - Longest register " "Info: - Longest clock path from clock \"kkk:inst\|altpll:altpll_component\|_clk0\" to source register is 2.279 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns kkk:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_1 24 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 24; CLK Node = 'kkk:inst\|altpll:altpll_component\|_clk0'" {  } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "" { kkk:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.568 ns) + CELL(0.711 ns) 2.279 ns clock3000000:inst3\|count\[5\] 2 REG LC_X15_Y5_N7 3 " "Info: 2: + IC(1.568 ns) + CELL(0.711 ns) = 2.279 ns; Loc. = LC_X15_Y5_N7; Fanout = 3; REG Node = 'clock3000000:inst3\|count\[5\]'" {  } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "2.279 ns" { kkk:inst|altpll:altpll_component|_clk0 clock3000000:inst3|count[5] } "NODE_NAME" } } { "clock3000000.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/clock3000000.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 31.20 % ) " "Info: Total cell delay = 0.711 ns ( 31.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.568 ns ( 68.80 % ) " "Info: Total interconnect delay = 1.568 ns ( 68.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "2.279 ns" { kkk:inst|altpll:altpll_component|_clk0 clock3000000:inst3|count[5] } "NODE_NAME" } } { "c:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/bin/Technology_Viewer.qrui" "2.279 ns" { kkk:inst|altpll:altpll_component|_clk0 {} clock3000000:inst3|count[5] {} } { 0.000ns 1.568ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "2.322 ns" { kkk:inst|altpll:altpll_component|_clk0 clock3000000:inst3|clkout } "NODE_NAME" } } { "c:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/bin/Technology_Viewer.qrui" "2.322 ns" { kkk:inst|altpll:altpll_component|_clk0 {} clock3000000:inst3|clkout {} } { 0.000ns 1.611ns } { 0.000ns 0.711ns } "" } } { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "2.279 ns" { kkk:inst|altpll:altpll_component|_clk0 clock3000000:inst3|count[5] } "NODE_NAME" } } { "c:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/bin/Technology_Viewer.qrui" "2.279 ns" { kkk:inst|altpll:altpll_component|_clk0 {} clock3000000:inst3|count[5] {} } { 0.000ns 1.568ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "clock3000000.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/clock3000000.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "clock3000000.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/clock3000000.vhd" 7 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "2.322 ns" { kkk:inst|altpll:altpll_component|_clk0 clock3000000:inst3|clkout } "NODE_NAME" } } { "c:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/bin/Technology_Viewer.qrui" "2.322 ns" { kkk:inst|altpll:altpll_component|_clk0 {} clock3000000:inst3|clkout {} } { 0.000ns 1.611ns } { 0.000ns 0.711ns } "" } } { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "2.279 ns" { kkk:inst|altpll:altpll_component|_clk0 clock3000000:inst3|count[5] } "NODE_NAME" } } { "c:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/bin/Technology_Viewer.qrui" "2.279 ns" { kkk:inst|altpll:altpll_component|_clk0 {} clock3000000:inst3|count[5] {} } { 0.000ns 1.568ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.186 ns - Longest register register " "Info: - Longest register to register delay is 7.186 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clock3000000:inst3\|count\[5\] 1 REG LC_X15_Y5_N7 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y5_N7; Fanout = 3; REG Node = 'clock3000000:inst3\|count\[5\]'" {  } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock3000000:inst3|count[5] } "NODE_NAME" } } { "clock3000000.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/clock3000000.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.272 ns) + CELL(0.838 ns) 2.110 ns clock3000000:inst3\|Add0~400 2 COMB LC_X15_Y8_N9 6 " "Info: 2: + IC(1.272 ns) + CELL(0.838 ns) = 2.110 ns; Loc. = LC_X15_Y8_N9; Fanout = 6; COMB Node = 'clock3000000:inst3\|Add0~400'" {  } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "2.110 ns" { clock3000000:inst3|count[5] clock3000000:inst3|Add0~400 } "NODE_NAME" } } { "clock3000000.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/clock3000000.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.679 ns) 2.789 ns clock3000000:inst3\|Add0~401 3 COMB LC_X15_Y7_N0 2 " "Info: 3: + IC(0.000 ns) + CELL(0.679 ns) = 2.789 ns; Loc. = LC_X15_Y7_N0; Fanout = 2; COMB Node = 'clock3000000:inst3\|Add0~401'" {  } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "0.679 ns" { clock3000000:inst3|Add0~400 clock3000000:inst3|Add0~401 } "NODE_NAME" } } { "clock3000000.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/clock3000000.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.625 ns) + CELL(0.590 ns) 5.004 ns clock3000000:inst3\|LessThan2~479 4 COMB LC_X15_Y5_N3 1 " "Info: 4: + IC(1.625 ns) + CELL(0.590 ns) = 5.004 ns; Loc. = LC_X15_Y5_N3; Fanout = 1; COMB Node = 'clock3000000:inst3\|LessThan2~479'" {  } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "2.215 ns" { clock3000000:inst3|Add0~401 clock3000000:inst3|LessThan2~479 } "NODE_NAME" } } { "clock3000000.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/clock3000000.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.249 ns) + CELL(0.442 ns) 6.695 ns clock3000000:inst3\|LessThan2~480 5 COMB LC_X15_Y6_N7 1 " "Info: 5: + IC(1.249 ns) + CELL(0.442 ns) = 6.695 ns; Loc. = LC_X15_Y6_N7; Fanout = 1; COMB Node = 'clock3000000:inst3\|LessThan2~480'" {  } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "1.691 ns" { clock3000000:inst3|LessThan2~479 clock3000000:inst3|LessThan2~480 } "NODE_NAME" } } { "clock3000000.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/clock3000000.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.309 ns) 7.186 ns clock3000000:inst3\|clkout 6 REG LC_X15_Y6_N8 29 " "Info: 6: + IC(0.182 ns) + CELL(0.309 ns) = 7.186 ns; Loc. = LC_X15_Y6_N8; Fanout = 29; REG Node = 'clock3000000:inst3\|clkout'" {  } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "0.491 ns" { clock3000000:inst3|LessThan2~480 clock3000000:inst3|clkout } "NODE_NAME" } } { "clock3000000.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/clock3000000.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.858 ns ( 39.77 % ) " "Info: Total cell delay = 2.858 ns ( 39.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.328 ns ( 60.23 % ) " "Info: Total interconnect delay = 4.328 ns ( 60.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "7.186 ns" { clock3000000:inst3|count[5] clock3000000:inst3|Add0~400 clock3000000:inst3|Add0~401 clock3000000:inst3|LessThan2~479 clock3000000:inst3|LessThan2~480 clock3000000:inst3|clkout } "NODE_NAME" } } { "c:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/bin/Technology_Viewer.qrui" "7.186 ns" { clock3000000:inst3|count[5] {} clock3000000:inst3|Add0~400 {} clock3000000:inst3|Add0~401 {} clock3000000:inst3|LessThan2~479 {} clock3000000:inst3|LessThan2~480 {} clock3000000:inst3|clkout {} } { 0.000ns 1.272ns 0.000ns 1.625ns 1.249ns 0.182ns } { 0.000ns 0.838ns 0.679ns 0.590ns 0.442ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "2.322 ns" { kkk:inst|altpll:altpll_component|_clk0 clock3000000:inst3|clkout } "NODE_NAME" } } { "c:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/bin/Technology_Viewer.qrui" "2.322 ns" { kkk:inst|altpll:altpll_component|_clk0 {} clock3000000:inst3|clkout {} } { 0.000ns 1.611ns } { 0.000ns 0.711ns } "" } } { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "2.279 ns" { kkk:inst|altpll:altpll_component|_clk0 clock3000000:inst3|count[5] } "NODE_NAME" } } { "c:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/bin/Technology_Viewer.qrui" "2.279 ns" { kkk:inst|altpll:altpll_component|_clk0 {} clock3000000:inst3|count[5] {} } { 0.000ns 1.568ns } { 0.000ns 0.711ns } "" } } { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "7.186 ns" { clock3000000:inst3|count[5] clock3000000:inst3|Add0~400 clock3000000:inst3|Add0~401 clock3000000:inst3|LessThan2~479 clock3000000:inst3|LessThan2~480 clock3000000:inst3|clkout } "NODE_NAME" } } { "c:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/bin/Technology_Viewer.qrui" "7.186 ns" { clock3000000:inst3|count[5] {} clock3000000:inst3|Add0~400 {} clock3000000:inst3|Add0~401 {} clock3000000:inst3|LessThan2~479 {} clock3000000:inst3|LessThan2~480 {} clock3000000:inst3|clkout {} } { 0.000ns 1.272ns 0.000ns 1.625ns 1.249ns 0.182ns } { 0.000ns 0.838ns 0.679ns 0.590ns 0.442ns 0.309ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}