clock3000000.vhd

来自「vhdl实现音乐播放,播放梁祝乐曲」· VHDL 代码 · 共 30 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clock3000000 is
  port(clkin:in std_logic;     
       clkout:buffer std_logic  
       );
end entity;

architecture arc of clock3000000 is
begin
 process(clkin)
 variable count:integer range 0 to 2999999;
  begin
    if (clkin'event and clkin='1') then
      if count>=2999999 then
	     count:=0;
      else
    	 count:=count+1;	
      end if;
      case count is
    	when 0 to 1499999=>clkout<='0';
    	when others =>clkout<='1';
      end case; 
   	end if;	
  end process;
end arc;