📄 notetabs.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity notetabs is
port ( clk: in std_logic;
toneindex: out std_logic_vector(3 downto 0)
);
end entity;
architecture one of notetabs is
component music_rom
port( address:in std_logic_vector(7 downto 0);
clock:in std_logic;
q:out std_logic_vector(3 downto 0));
end component;
signal counter: std_logic_vector(7 downto 0);
begin
cnt8:process(clk,counter)
begin
if counter=138 then
counter<="00000000";
elsif(clk'event and clk='1')then
counter<=counter+1;
end if;
end process;
u1:music_rom port map(address=>counter,q=>toneindex,clock=>clk);
end one;
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