block1.tan.rpt

vhdl实现音乐播放,播放梁祝乐曲

; Worst-case th                                         ; N/A       ; None                             ; 2.766 ns                         ; altera_internal_jtag~TDIUTAP                                                                                                  ; notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[3] ; --                                     ; altera_internal_jtag~TCKUTAP           ; 0            ;
; Clock Setup: 'kkk:inst|altpll:altpll_component|_clk0' ; 34.262 ns ; 24.00 MHz ( period = 41.666 ns ) ; 135.06 MHz ( period = 7.404 ns ) ; clock3000000:inst3|count[5]                                                                                                   ; clock3000000:inst3|clkout                                                                                                                                                          ; kkk:inst|altpll:altpll_component|_clk0 ; kkk:inst|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'           ; N/A       ; None                             ; 67.12 MHz ( period = 14.898 ns ) ; sld_hub:sld_hub_inst|HUB_BYPASS_REG                                                                                           ; sld_hub:sld_hub_inst|hub_tdo_reg                                                                                                                                                   ; altera_internal_jtag~TCKUTAP           ; altera_internal_jtag~TCKUTAP           ; 0            ;
; Clock Hold: 'kkk:inst|altpll:altpll_component|_clk0'  ; -4.124 ns ; 24.00 MHz ( period = 41.666 ns ) ; N/A                              ; notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|altsyncram_8962:altsyncram1|q_a[2] ; ToneTaba:inst6|Tone[10]                                                                                                                                                            ; kkk:inst|altpll:altpll_component|_clk0 ; kkk:inst|altpll:altpll_component|_clk0 ; 42           ;
; Total number of failed paths                          ;           ;                                  ;                                  ;                                                                                                                               ;                                                                                                                                                                                    ;                                        ;                                        ; 42           ;
+-------------------------------------------------------+-----------+----------------------------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+--------------+


+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                      ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                         ; Setting            ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; Off                ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                         ;
+----------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                        ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+----------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; kkk:inst|altpll:altpll_component|_clk0 ;                    ; PLL output ; 24.0 MHz         ; 0.000 ns      ; 0.000 ns     ; inclk    ; 6                     ; 5                   ; -1.833 ns ;              ;
; inclk                                  ;                    ; User Pin   ; 20.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; altera_internal_jtag~TCKUTAP           ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+----------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'kkk:inst|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                           ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------+-------------------------------------+----------------------------------------+----------------------------------------+-----------------------------+---------------------------+-------------------------+