📄 block1.map.rpt
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; |altpll:altpll_component| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |Block1|kkk:inst|altpll:altpll_component ; work ;
; |notetabs:inst4| ; 71 (11) ; 38 ; 1024 ; 0 ; 0 ; 33 (3) ; 4 (0) ; 34 (8) ; 20 (7) ; 0 (0) ; |Block1|notetabs:inst4 ; work ;
; |music_rom:u1| ; 60 (0) ; 30 ; 1024 ; 0 ; 0 ; 30 (0) ; 4 (0) ; 26 (0) ; 13 (0) ; 0 (0) ; |Block1|notetabs:inst4|music_rom:u1 ; work ;
; |altsyncram:altsyncram_component| ; 60 (0) ; 30 ; 1024 ; 0 ; 0 ; 30 (0) ; 4 (0) ; 26 (0) ; 13 (0) ; 0 (0) ; |Block1|notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component ; work ;
; |altsyncram_gq41:auto_generated| ; 60 (0) ; 30 ; 1024 ; 0 ; 0 ; 30 (0) ; 4 (0) ; 26 (0) ; 13 (0) ; 0 (0) ; |Block1|notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated ; work ;
; |altsyncram_8962:altsyncram1| ; 0 (0) ; 0 ; 1024 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |Block1|notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|altsyncram_8962:altsyncram1 ; work ;
; |sld_mod_ram_rom:mgl_prim2| ; 60 (34) ; 30 ; 0 ; 0 ; 0 ; 30 (13) ; 4 (4) ; 26 (17) ; 13 (8) ; 0 (0) ; |Block1|notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|sld_mod_ram_rom:mgl_prim2 ; work ;
; |sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr| ; 26 (26) ; 9 ; 0 ; 0 ; 0 ; 17 (17) ; 0 (0) ; 9 (9) ; 5 (5) ; 0 (0) ; |Block1|notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr ; work ;
; |sld_hub:sld_hub_inst| ; 106 (25) ; 70 ; 0 ; 0 ; 0 ; 36 (18) ; 16 (0) ; 54 (7) ; 5 (0) ; 0 (0) ; |Block1|sld_hub:sld_hub_inst ; work ;
; |lpm_decode:instruction_decoder| ; 5 (0) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (0) ; 0 (0) ; 0 (0) ; |Block1|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder ; work ;
; |decode_ogi:auto_generated| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; 0 (0) ; 0 (0) ; |Block1|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_ogi:auto_generated ; work ;
; |lpm_shiftreg:jtag_ir_register| ; 10 (10) ; 10 ; 0 ; 0 ; 0 ; 0 (0) ; 10 (10) ; 0 (0) ; 0 (0) ; 0 (0) ; |Block1|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register ; work ;
; |sld_dffex:BROADCAST| ; 2 (2) ; 1 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |Block1|sld_hub:sld_hub_inst|sld_dffex:BROADCAST ; work ;
; |sld_dffex:IRF_ENA_0| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |Block1|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0 ; work ;
; |sld_dffex:IRF_ENA| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |Block1|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA ; work ;
; |sld_dffex:IRSR| ; 9 (9) ; 6 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; 0 (0) ; 0 (0) ; |Block1|sld_hub:sld_hub_inst|sld_dffex:IRSR ; work ;
; |sld_dffex:RESET| ; 2 (2) ; 1 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |Block1|sld_hub:sld_hub_inst|sld_dffex:RESET ; work ;
; |sld_dffex:\GEN_IRF:1:IRF| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; 0 (0) ; 0 (0) ; |Block1|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF ; work ;
; |sld_dffex:\GEN_SHADOW_IRF:1:S_IRF| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 5 (5) ; 0 (0) ; 0 (0) ; 0 (0) ; |Block1|sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF ; work ;
; |sld_jtag_state_machine:jtag_state_machine| ; 21 (21) ; 19 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 19 (19) ; 0 (0) ; 0 (0) ; |Block1|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine ; work ;
; |sld_rom_sr:HUB_INFO_REG| ; 20 (20) ; 9 ; 0 ; 0 ; 0 ; 11 (11) ; 0 (0) ; 9 (9) ; 5 (5) ; 0 (0) ; |Block1|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG ; work ;
+------------------------------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+-----------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+------+----------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+-----------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+------+----------+
; notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|altsyncram_8962:altsyncram1|ALTSYNCRAM ; AUTO ; True Dual Port ; 256 ; 4 ; 256 ; 4 ; 1024 ; date.hex ;
+-----------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+------+----------+
+----------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches ;
+-----------------------------------------------------+---------------------+------------------------+
; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
+-----------------------------------------------------+---------------------+------------------------+
; ToneTaba:inst6|Tone[0] ; ToneTaba:inst6|Mux4 ; yes ;
; ToneTaba:inst6|Tone[1] ; ToneTaba:inst6|Mux4 ; yes ;
; ToneTaba:inst6|Tone[2] ; ToneTaba:inst6|Mux4 ; yes ;
; ToneTaba:inst6|Tone[3] ; ToneTaba:inst6|Mux4 ; yes ;
; ToneTaba:inst6|Tone[4] ; ToneTaba:inst6|Mux4 ; yes ;
; ToneTaba:inst6|Tone[5] ; ToneTaba:inst6|Mux4 ; yes ;
; ToneTaba:inst6|Tone[6] ; ToneTaba:inst6|Mux4 ; yes ;
; ToneTaba:inst6|Tone[7] ; ToneTaba:inst6|Mux4 ; yes ;
; ToneTaba:inst6|Tone[8] ; ToneTaba:inst6|Mux4 ; yes ;
; ToneTaba:inst6|Tone[9] ; ToneTaba:inst6|Mux4 ; yes ;
; ToneTaba:inst6|Tone[10] ; ToneTaba:inst6|Mux4 ; yes ;
; Number of user-specified and inferred latches = 11 ; ; ;
+-----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+--------------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+---------------------------------------+----------------------------------------------+
; Register name ; Reason for Removal ;
+---------------------------------------+----------------------------------------------+
; Speakera:inst5|SpkS ; Merged with Speakera:inst5|\DelaySpkS:Count2 ;
; Total Number of Removed Registers = 1 ; ;
+---------------------------------------+----------------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 151 ;
; Number of registers using Synchronous Clear ; 21 ;
; Number of registers using Synchronous Load ; 19 ;
; Number of registers using Asynchronous Clear ; 63 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 60 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; sld_hub:sld_hub_inst|hub_tdo_reg ; 2 ;
; Total number of inverted registers = 1 ; ;
+----------------------------------------+---------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |Block1|notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0] ;
; 5:1 ; 5 bits ; 15 LEs ; 5 LEs ; 10 LEs ; Yes ; |Block1|notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|word_counter[0] ;
; 24:1 ; 4 bits ; 64 LEs ; 48 LEs ; 16 LEs ; Yes ; |Block1|notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0] ;
; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |Block1|sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0] ;
; 5:1 ; 5 bits ; 15 LEs ; 5 LEs ; 10 LEs ; Yes ; |Block1|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0] ;
; 20:1 ; 4 bits ; 52 LEs ; 32 LEs ; 20 LEs ; Yes ; |Block1|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|altsyncram_8962:altsyncram1 ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr ;
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