counter.txt

开发环境是FPGA开发工具

我们知道格雷码计数的特点就是相邻的码字只有一个比特不同,那么我们在设计格雷码计数时找到这个比特取反就是了。找到这个比特的思路: 
      先将格雷码换算成二进制码,此二进制码中从LSB到MSB第一个为''0''的比特对应的格雷码位置即为所需位置,如果全''1''则MSB的位置为所需位置。
      下面以循环格雷码为例,给出一个VHDL程序。
      Library ieee;
      Use ieee.std_logic_1164.all;
      Entity Demo is Port(
      clock :in std_logic;
      q ： out std_logic_vector(3 downto 0)); --vector的长度随用户而定,这里只是一个示例。
      End Demo;
      Architecture myFavor of Demo is
      Function NxG(argv :std_logic_vector) return std_logic_vector is 
      --此函数完成输入一个格雷码返回下一个数的格雷码
      alias GV :std_logic_vector(1 to argv''length) is argv;
      variable BV,GC :std_logic_vector(1 to argv''length);
      Begin
      BV(1) := GV(1);
      for i in 2 to argv''length loop
      BV(i) := GV(i) xor BV(i - 1);
      end loop;
      GC := GV;
      for i in argv''length downto 1 loop
      if BV(i) = ''0'' or i = 1 then
      GC(i) := not GC(i);
      exit;
      end if; 
      end loop;
      return GC;
      End NxG;
      Signal GC :std_logic_vector(3 downto 0);
      Begin
      Process(clock) begin
      if rising_edge(clock) then
      GC <= NxG(GC);
      end if;
      End process;
      q <= GC;
      End myFavor；





   Library ieee;
   Use ieee.std_logic_1164.all;
     Entity counter is 
        Port(clock :in std_logic;
                 q :out std_logic_vector(3 downto 0)); 
      End counter;
     

   Architecture myFavor of counter is
    
      Function NxG(argv :std_logic_vector) return std_logic_vector is
      
      alias GV :std_logic_vector(1 to argv'length) is argv;
      variable BV,GC :std_logic_vector(1 to argv'length);
      Begin
      BV(1) := GV(1);
      for i in 2 to argv'length loop
      BV(i) := GV(i) xor BV(i - 1);
      end loop;
      GC := GV;
      for i in argv'length downto 1 loop
      if BV(i) = '0' or i = 1 then
      GC(i) := not GC(i);
      
      exit;
      end if; 
      end loop;
      return GC;
      End NxG;
      Signal GC :std_logic_vector(3 downto 0);
      begin
      Process(clock) 
      begin
      if rising_edge(clock) then
      GC <= NxG(GC);
      end if;
      End process;
      q <= GC;
      End myFavor;