📄 addvb_models_7.v.txt
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if (rst == 0) state <= S_idle; else state <= next_state; end
/* always @ (state or instruction or zero) begin: Output_and_next_state
Note: The above event control expression leads to incorrect operation. The state transition causes the activity to be evaluated once, then the resulting instruction change causes it to be evaluated again, but with the residual value of opcode. On the second pass the value seen is the value opcode had before the state change, which results in Sel_PC = 0 in state 3, which will cause a return to state 1 at the next clock. Finally, opcode is changed, but this does not trigger a re-evaluation because it is not in the event control expression. So, the caution is to be sure to use opcode in the event control expression. That way, the final execution of the behavior uses the value of opcode that results from the state change, and leads to the correct value of Sel_PC.
*/
always @ (state or opcode or src or dest or zero) begin: Output_and_next_state
Sel_R0 = 0; Sel_R1 = 0; Sel_R2 = 0; Sel_R3 = 0; Sel_PC = 0;
Load_R0 = 0; Load_R1 = 0; Load_R2 = 0; Load_R3 = 0; Load_PC = 0;
Load_IR = 0; Load_Add_R = 0; Load_Reg_Y = 0; Load_Reg_Z = 0;
Inc_PC = 0;
Sel_Bus_1 = 0;
Sel_ALU = 0;
Sel_Mem = 0;
write = 0;
err_flag = 0; // Used for de-bug in simulation
next_state = state;
case (state) S_idle: next_state = S_fet1;
S_fet1: begin
next_state = S_fet2;
Sel_PC = 1;
Sel_Bus_1 = 1;
Load_Add_R = 1;
end
S_fet2: begin
next_state = S_dec;
Sel_Mem = 1;
Load_IR = 1;
Inc_PC = 1;
end
S_dec: case (opcode)
NOP: next_state = S_fet1;
ADD, SUB, AND: begin
next_state = S_ex1;
Sel_Bus_1 = 1;
Load_Reg_Y = 1;
case (src)
R0: Sel_R0 = 1;
R1: Sel_R1 = 1;
R2: Sel_R2 = 1;
R3: Sel_R3 = 1;
default : err_flag = 1;
endcase
end // ADD, SUB, AND
NOT: begin
next_state = S_fet1;
Load_Reg_Z = 1;
Sel_Bus_1 = 1;
Sel_ALU = 1;
case (src)
R0: Sel_R0 = 1;
R1: Sel_R1 = 1;
R2: Sel_R2 = 1;
R3: Sel_R3 = 1;
default : err_flag = 1;
endcase
case (dest)
R0: Load_R0 = 1;
R1: Load_R1 = 1;
R2: Load_R2 = 1;
R3: Load_R3 = 1;
default: err_flag = 1;
endcase
end // NOT
RD: begin
next_state = S_rd1;
Sel_PC = 1; Sel_Bus_1 = 1; Load_Add_R = 1;
end // RD
WR: begin
next_state = S_wr1;
Sel_PC = 1; Sel_Bus_1 = 1; Load_Add_R = 1;
end // WR
BR: begin
next_state = S_br1;
Sel_PC = 1; Sel_Bus_1 = 1; Load_Add_R = 1;
end // BR
BRZ: if (zero == 1) begin
next_state = S_br1;
Sel_PC = 1; Sel_Bus_1 = 1; Load_Add_R = 1;
end // BRZ
else begin
next_state = S_fet1;
Inc_PC = 1;
end
default : next_state = S_halt;
endcase // (opcode)
S_ex1: begin
next_state = S_fet1;
Load_Reg_Z = 1;
Sel_ALU = 1;
case (dest)
R0: begin Sel_R0 = 1; Load_R0 = 1; end
R1: begin Sel_R1 = 1; Load_R1 = 1; end
R2: begin Sel_R2 = 1; Load_R2 = 1; end
R3: begin Sel_R3 = 1; Load_R3 = 1; end
default : err_flag = 1;
endcase
end
S_rd1: begin
next_state = S_rd2;
Sel_Mem = 1;
Load_Add_R = 1;
Inc_PC = 1;
end
S_wr1: begin
next_state = S_wr2;
Sel_Mem = 1;
Load_Add_R = 1;
Inc_PC = 1;
end
S_rd2: begin
next_state = S_fet1;
Sel_Mem = 1;
case (dest)
R0: Load_R0 = 1;
R1: Load_R1 = 1;
R2: Load_R2 = 1;
R3: Load_R3 = 1;
default : err_flag = 1;
endcase
end
S_wr2: begin
next_state = S_fet1;
write = 1;
case (src)
R0: Sel_R0 = 1;
R1: Sel_R1 = 1;
R2: Sel_R2 = 1;
R3: Sel_R3 = 1;
default : err_flag = 1;
endcase
end
S_br1: begin next_state = S_br2; Sel_Mem = 1; Load_Add_R = 1; end
S_br2: begin next_state = S_fet1; Sel_Mem = 1; Load_PC = 1; end
S_halt: next_state = S_halt;
default: next_state = S_idle;
endcase
end
endmodule
module Memory_Unit (data_out, data_in, address, clk, write);
parameter word_size = 8;
parameter memory_size = 256;
output [word_size-1: 0] data_out;
input [word_size-1: 0] data_in;
input [word_size-1: 0] address;
input clk, write;
reg [word_size-1: 0] memory [memory_size-1: 0];
assign data_out = memory[address];
always @ (posedge clk)
if (write) memory[address] = data_in;
endmodule
module test_RISC_SPM ();
reg rst;
wire clk;
parameter word_size = 8;
reg [8: 0] k;
Clock_Unit M1 (clk);
RISC_SPM M2 (clk, rst);
// define probes
wire [word_size-1: 0] word0, word1, word2, word3, word4, word5, word6;
wire [word_size-1: 0] word7, word8, word9, word10, word11, word12, word13;
wire [word_size-1: 0] word14;
wire [word_size-1: 0] word128, word129, word130, word131, word132, word255;
wire [word_size-1: 0] word133, word134, word135, word136, word137;
wire [word_size-1: 0] word138, word139, word140;
assign word0 = M2.M2_SRAM.memory[0];
assign word1 = M2.M2_SRAM.memory[1];
assign word2 = M2.M2_SRAM.memory[2];
assign word3 = M2.M2_SRAM.memory[3];
assign word4 = M2.M2_SRAM.memory[4];
assign word5 = M2.M2_SRAM.memory[5];
assign word6 = M2.M2_SRAM.memory[6];
assign word7 = M2.M2_SRAM.memory[7];
assign word8 = M2.M2_SRAM.memory[8];
assign word9 = M2.M2_SRAM.memory[9];
assign word10 = M2.M2_SRAM.memory[10];
assign word11 = M2.M2_SRAM.memory[11];
assign word12 = M2.M2_SRAM.memory[12];
assign word13 = M2.M2_SRAM.memory[13];
assign word14 = M2.M2_SRAM.memory[14];
assign word128 = M2.M2_SRAM.memory[128];
assign word129 = M2.M2_SRAM.memory[129];
assign word130 = M2.M2_SRAM.memory[130];
assign word131 = M2.M2_SRAM.memory[131];
assign word132 = M2.M2_SRAM.memory[132];
assign word133 = M2.M2_SRAM.memory[133];
assign word134 = M2.M2_SRAM.memory[134];
assign word135 = M2.M2_SRAM.memory[135];
assign word136 = M2.M2_SRAM.memory[136];
assign word137 = M2.M2_SRAM.memory[137];
assign word138 = M2.M2_SRAM.memory[138];
assign word139 = M2.M2_SRAM.memory[139];
assign word140 = M2.M2_SRAM.memory[140];
assign word255 = M2.M2_SRAM.memory[255];
initial #2800 $finish;
Flush Memory
initial begin: Flush_Memory
#2 rst = 0; for (k=0; k<=255; k=k+1)M2.M2_SRAM.memory[k] = 0; #10 rst = 1;
end
initial begin: Load_program
#5
// opcode_src_dest
M2.M2_SRAM.memory[0] = 8'b0000_00_00; // NOP
M2.M2_SRAM.memory[1] = 8'b0101_00_10; // Read 130 to R2
M2.M2_SRAM.memory[2] = 130;
M2.M2_SRAM.memory[3] = 8'b0101_00_11; // Read 131 to R3
M2.M2_SRAM.memory[4] = 131;
M2.M2_SRAM.memory[5] = 8'b0101_00_01; // Read 128 to R1
M2.M2_SRAM.memory[6] = 128;
M2.M2_SRAM.memory[7] = 8'b0101_00_00; // Read 129 to R0
M2.M2_SRAM.memory[8] = 129;
M2.M2_SRAM.memory[9] = 8'b0010_00_01; // Sub R1-R0 to R1
M2.M2_SRAM.memory[10] = 8'b1000_00_00; // BRZ
M2.M2_SRAM.memory[11] = 134; // Holds address for BRZ
M2.M2_SRAM.memory[12] = 8'b0001_10_11; // Add R2+R3 to R3
M2.M2_SRAM.memory[13] = 8'b0111_00_11; // BR
M2.M2_SRAM.memory[14] = 140;
// Load data
M2.M2_SRAM.memory[128] = 6;
M2.M2_SRAM.memory[129] = 1;
M2.M2_SRAM.memory[130] = 2;
M2.M2_SRAM.memory[131] = 0;
M2.M2_SRAM.memory[134] = 139;
//M2.M2_SRAM.memory[135] = 0;
M2.M2_SRAM.memory[139] = 8'b1111_00_00; // HALT
M2.M2_SRAM.memory[140] = 9; // Recycle
end
endmodule
module UART_Transmitter_Arch
(Serial_out, Data_Bus, Byte_ready, Load_XMT_datareg, T_byte, Clock, reset_);
parameter word_size = 8; // Size of data word, e.g., 8 bits
parameter one_hot_count = 3; // Number of one-hot states
parameter state_count = one_hot_count; // Number of bits in state register
parameter size_bit_count = 3; // Size of the bit counter, e.g., 4
// Must count to word_size + 1
parameter idle = 3'b001; // one-hot state encoding
parameter waiting = 3'b010;
parameter sending = 3'b100;
parameter all_ones = 9'b1_1111_1111; // Word + 1 extra bit
output Serial_out; // Serial output to data channel
input [word_size - 1 : 0] Data_Bus; // Host data bus containing data word
input Byte_ready; // Used by host to signal ready
input Load_XMT_datareg; // Used by host to load the data register
input T_byte; // Used by host to signal start of transmission
input Clock; // Bit clock of the transmitter
input reset_; // Resets internal registers, loads the
// XMT_shftreg with ones
reg [word_size -1: 0] XMT_datareg; // Transmit Data Register
reg [word_size: 0] XMT_shftreg; // Transmit Shift Register: {data, start bit}
reg Load_XMT_shftreg; // Flag to load the XMT_shftreg
reg [state_count -1: 0] state, next_state; // State machine controller
reg [size_bit_count: 0] bit_count; // Counts the bits that are transmitted
reg clear; // Clears bit_count after last bit is sent
reg shift; // Causes shift of data in XMT_shftreg
reg start; // Signals start of transmission
assign Serial_out = XMT_shftreg[0]; // LSB of shift register
always @ (state or Byte_ready or bit_count or T_byte) begin: Output_and_next_state
Load_XMT_shftreg = 0;
clear = 0;
shift = 0;
start = 0;
next_state = state;
case (state)
idle: if (Byte_ready == 1) begin
Load_XMT_shftreg = 1;
next_state = waiting;
end
waiting: if (T_byte == 1) begin
start = 1;
next_state = sending;
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