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odt_enabled = 0;
end // Report the additive latency value if ((ext_mode_reg_1[5:3] >= al_min) && (ext_mode_reg_1[5:3] <= al_max)) begin if (debug) $display ("%m: at time %t EMR : Additive Latency = %d", $time, ext_mode_reg_1[5:3]); add_latency_clocks = ext_mode_reg_1[5:3]; end else begin $display ("%m: at time %t ERROR: ADDITIVE LATENCY SPECIFIED NOT SUPPORTED", $time); end // Report the DQS_N Enable Status if (!ext_mode_reg_1[10]) begin if (debug) $display ("%m: at time %t EMR : DQS_N Enabled", $time); dqs_n_enabled = 1; end else begin if (debug) $display ("%m: at time %t EMR : DQS_N Disabled", $time); dqs_n_enabled = 0; end // Report the RDQS Enable Status if (ext_mode_reg_1[11]) begin if (debug) $display ("%m: at time %t EMR : RDQS Enabled", $time); rdqs_enabled = 1; if ((DQ_BITS == 4) || (DQ_BITS == 16)) $display ("%m: at time %t ERROR: RDQS Enabled - RDQS doesn't exist in a x4 or x16 part", $time); end else begin if (debug) $display ("%m: at time %t EMR : RDQS Disabled", $time); rdqs_enabled = 0; end // Report Output Enable/Disable Status
if (!ext_mode_reg_1[12]) begin
if (debug) $display ("%m: at time %t EMR : Outputs Enabled", $time); outputs_enabled = 1; end else begin
if (debug) $display ("%m: at time %t EMR : Outputs Disabled", $time); outputs_enabled = 0; end
// Check for reserved bits being used if (ext_mode_reg_1[14:13] !== 4'h0) begin $display ("%m: at time %t ERROR : Reserved bits in EMR must be programmed to zero.", $time); end end 2 : begin ext_mode_reg_2 = addr_in; // FILL THE EXTENDED MODE REGISTER 2 if (debug) $display ("%m: at time %t EMR : Load Extended Mode Register 2", $time); // Check for reserved bits being used if (ext_mode_reg_2[12:0] !== 0) begin $display ("%m: at time %t ERROR : Reserved bits in EMR 2 must be programmed to zero.", $time); end ext_mode_reg_2_set = 1; end 3 : begin ext_mode_reg_3 = addr_in; // FILL THE EXTENDED MODE REGISTER 3 if (debug) $display ("%m: at time %t EMR : Load Extended Mode Register 3", $time); // Check for reserved bits being used if (ext_mode_reg_3 !== 0) begin $display ("%m: at time %t ERROR : Reserved bits in EMR 3 must be programmed to zero.", $time); end ext_mode_reg_3_set = 1; end endcase end else begin
$display ("%m: at time %t ERROR: All banks must be Precharged before Load Mode Register Command", $time);
if (!no_halt) $stop (0);
end
tmrd_chk <= $time;
end
`REF : begin // Auto Refresh
if (tmrd_chk > 0) if (tmrd_chk + tmrd*tck > $time)
$display ("%m: at time %t ERROR: tMRD violation during Auto Refresh", $time);
if (trfc_chk > 0) if (trfc_chk + trfc_min > $time) $display ("%m: at time %t ERROR: tRFC violation during Auto Refresh", $time); for (i=0; i<(1<<BA_BITS); i=i+1) begin
if (trp_chk[i] > 0) if (trp_chk[i] + trp > $time) $display ("%m: at time %t ERROR: tRP violation during Auto Refresh", $time); end
if (trpa_chk > 0) if ((trpa_chk + trpa > $time)) $display ("%m: at time %t ERROR: tRPA violation during Auto Refresh", $time); for (i=0; i<(1<<BA_BITS); i=i+1) begin
if (trc_chk[i] > 0) if (trc_chk[i] + trc > $time)
$display ("%m: at time %t ERROR: tRC violation during Auto Refresh", $time);
end
if (txp_chk + txp*tck > $time) $display ("%m: at time %t ERROR: tXP violation during Auto Refresh", $time); if (($time > txsnr) && (txs_chk + txsnr > $time) ) $display ("%m: at time %t ERROR: tXSNR violation during Auto Refresh", $time); if (&precharged_banks) begin // All banks precharged? // Display Debug Message if (debug) $display ("%m: at time %t AREF : Auto Refresh", $time); end else begin $display ("%m: at time %t ERROR: All banks must be Precharged before an Auto Refresh", $time); if (!no_halt) $stop (0); end trfc_chk = $time; trfc_max_violation = 0; aref_count <= aref_count + 1; end
`PRE : begin // Precharge
if (auto_precharge[ba_in]) begin $display ("%m: at time %t ERROR: Cannot Precharge - Auto Precharge is scheduled to Bank %d", $time, ba_in); if (!no_halt) $stop (0); end else begin if (addr_in[10]) begin
if (debug) $display ("%m: at time %t PRE : Precharge All Banks", $time); end else begin
if (debug) $display ("%m: at time %t PRE : Precharge Bank %d", $time, ba_in); end
for (i=0; i<(1<<BA_BITS); i=i+1) begin if (activated_banks[i] && (addr_in[10] || (i == ba_in))) begin if (tmrd_chk > 0) if (tmrd_chk + tmrd*tck > $time) $display ("%m: at time %t ERROR: tMRD violation during Precharge", $time); if (trfc_chk > 0) if (trfc_chk + trfc_min > $time) $display ("%m: at time %t ERROR: tRFC violation during Precharge", $time); if (tras_chk[i] > 0) if (tras_chk[i] + tras_min > $time) $display ("%m: at time %t ERROR: tRAS minimum violation during Precharge to Bank %d", $time, i); if (twr_chk[i] > 0) if ((twr_chk[i] + (write_latency + burst_clocks)*tck + twr) > $time) $display ("%m: at time %t ERROR: tWR violation during Precharge to Bank %d", $time, i); if (trtp_chk[i] > 0) if ((trtp_chk[i] + (add_latency_clocks + burst_clocks - 2)*tck + trtp) > $time) $display ("%m: at time %t ERROR: tRTP violation during Precharge to Bank %d", $time, i); if (trtp_chk[i] > 0) if ((trtp_chk[i] + (add_latency_clocks + 2)*tck) > $time) $display ("%m: at time %t ERROR: Read to Precharge violation during Precharge to Bank %d", $time, i); if (txp_chk + txp*tck > $time) $display ("%m: at time %t ERROR: tXP violation during Precharge", $time); if (($time > txsnr) && (txs_chk + txsnr > $time)) $display ("%m: at time %t ERROR: tXSNR violation during Precharge", $time); activated_banks[i] = 1'b0; trp_chk[i] = $time; if (addr_in[10]) begin trpa_chk = $time; end end end end
end
`ACT : begin // Activate if (!(power_up_done)) begin
$display ("%m: at time %t ERROR: Power Up and Initialization Sequence not complete", $time);
if (!no_halt) $stop (0);
end
if (tmrd_chk > 0) if (tmrd_chk + tmrd*tck > $time)
$display ("%m: at time %t ERROR: tMRD violation during Activate", $time);
if (trfc_chk > 0) if (trfc_chk + trfc_min > $time) $display ("%m: at time %t ERROR: tRFC violation during Activate", $time); if (trp_chk[ba_in] > 0) if (trp_chk[ba_in] + trp > $time) $display ("%m: at time %t ERROR: tRP violation during Activate to Bank %d", $time, ba_in); if (trpa_chk > 0) if (trpa_chk + trpa > $time) $display ("%m: at time %t ERROR: tRPA violation during Activate to Bank %d", $time, ba_in); if (trc_chk[ba_in] > 0) if (trc_chk[ba_in] + trc > $time) $display ("%m: at time %t ERROR: tRC violation during Activate to Bank %d", $time, ba_in);
if (trrd_chk > 0) if ((previous_bank != ba_in) && (trrd_chk + trrd > $time))
$display ("%m: at time %t ERROR: tRRD violation during Activate bank = %d", $time, ba_in);
if (txp_chk + txp*tck > $time) $display ("%m: at time %t ERROR: tXP violation during Activate", $time); if (($time > txsnr) && (txs_chk + txsnr > $time)) $display ("%m: at time %t ERROR: tXSNR violation during Activate", $time); if (precharged_banks[ba_in]) begin activated_banks[ba_in] = 1'b1; precharged_banks[ba_in] = 1'b0; bank_row_addr[ba_in] = addr_in; if (debug) $display ("%m: at time %t ACT : Bank = %d Row = %d",$time, ba_in, addr_in); end else begin $display ("%m: at time %t ERROR: Activate to Bank %d Failed, Bank %d is not Precharged.", $time, ba_in, ba_in); if (!no_halt) $stop (0); end tras_chk[ba_in] = $time;
trcd_chk[ba_in] = $time;
trc_chk[ba_in] = $time;
trrd_chk = $time;
previous_bank = ba_in;
// Check to make sure that the 8 bank devices don't have more that 4 sequential activates within a (4*tRRD + 2*tCK) window of time
if ((1<<BA_BITS) == 8) begin
num_activated_banks = 0;
for (i=0; i<(1<<BA_BITS); i=i+1) begin
if (tras_chk[i] + tfaw > $time) begin
num_activated_banks = num_activated_banks + 1;
end
end
if (num_activated_banks > 4) $display ("%m: at time %t ERROR: tFAW violation during Activate to Bank %d", $time, ba_in[BA_BITS -1 : 0]);
end
end
`WRITE : begin // Write if (!(power_up_done)) begin $display ("%m: at time %t ERROR: Power Up and Initialization Sequence not complete", $time); if (!no_halt) $stop (0); end if (tmrd_chk > 0) if (tmrd_chk + tmrd*tck > $time) $display ("%m: at time %t ERROR: tMRD violation during Write", $time); if (trfc_chk > 0) if (trfc_chk + trfc_min > $time) $display ("%m: at time %t ERROR: tRFC violation during Write", $time); if (trp_chk[ba_in] > 0) if (trp_chk[ba_in] + trp > $time) $display ("%m: at time %t ERROR: tRP violation during Write", $time); if (trpa_chk > 0) if (trpa_chk + trpa > $time) $display ("%m: at time %t ERROR: tRPA violation during Write", $time); if (trcd_chk[ba_in] > 0) if (trcd_chk[ba_in] - add_latency_clocks*tck + trcd > $time) $display ("%m: at time %t ERROR: tRCD violation during Write to Bank %d", $time, ba_in); if (tccd_chk > 0) if (tccd_chk + (tccd*tck) > $time) $display ("%m: at time %t ERROR: tCCD violation during Write to Bank %d", $time, ba_in); if (trtw_chk > 0) if (trtw_chk + (read_latency + burst_clocks + 1 - write_latency)*tck > $time) $display ("%m: at time %t ERROR: tRTW violation during Write", $time); if (txp_chk + txp*tck > $time) $display ("%m: at time %t ERROR: tXP violation during Write", $time); if (($time > txsnr) && (txs_chk + txsnr > $time)) $display ("%m: at time %t ERROR: tXSNR violation during Write", $time); if (auto_precharge[ba_in]) begin $display ("%m: at time %t ERROR: Cannot Write - Auto Precharge is scheduled to Bank %d", $time, ba_in); if (!no_halt) $stop (0); end else if (!activated_banks[ba_in]) begin $display ("%m: at time %t ERROR: Cannot Write - Bank %d is not Activated", $time, ba_in); if (!no_halt) $stop (0); end else if ((command[write_latency*2-2] == `WRITE) || ((burst_clocks == 4) && (command[write_latency*2-6] == `⌨️ 快捷键说明
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