📄 ddr2.v
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/****************************************************************************************
*
* File Name: ddr2.v
* Version: 3.00
* Model: BUS Functional
*
* Dependencies: ddr2_parameters.v
*
* Description: Micron SDRAM DDR2 (Double Data Rate 2)
*
* Limitation: - Doesn't check for refresh timings, except during Power Down
* - Model assumes CLK and CLK_N crossing at same edges
* - Model assumes DQS and DQS_N crossing at same edges
* - Test Mode is not supported*
* Note: - Set simulator resolution to "ps" accuracy
* - Set Debug = 0 to disable $display messages
*
* Disclaimer This software code and all associated documentation, comments or other
* of Warranty: information (collectively "Software") is provided "AS IS" without
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGES. Because some jurisdictions prohibit the exclusion or
* limitation of liability for consequential or incidental damages, the
* above limitation may not apply to you.
*
* Copyright 2003 Micron Technology, Inc. All rights reserved.
*
* Rev Author Date Changes
* ---------------------------------------------------------------------------------------
* 1.00 JMK 07/29/03 Initial Release* 1.10 JMK 08/09/03 Timing Parameter updates to tIS, tIH, tDS, tDH* 2.20 JMK 08/07/03 General cleanup* 2.30 JMK 11/26/03 Added cl_min, cl_max, wl_min and wl_max parameters.* Added al_min and al_max parameters.* Removed support for OCD.* 2.40 JMK 01/15/04 Removed verilog 2001 constructs.* 2.50 JMK 01/29/04 Removed tRP checks during Precharge command.* 2.60 JMK 04/20/04 Fixed tWTR check.* 2.70 JMK 04/30/04 Added tRFC maximum check.* Combined Self Refresh and Power Down always blocks.* Added Reset Function (CKE LOW Anytime).* 2.80 JMK 08/19/04 Precharge is treated as NOP when bank is not active. * Added checks for tRAS, tWR, tRTP to any bank during Pre-All.* tRFC maximum violation will only display one time.* 2.90 JMK 11/05/04 Fixed DQS checking during write.* Fixed false tRFC max assertion during power up and self ref.* Added warning for 200us CKE low time during initialization.* Added -3, -3E, and -37V speed grades to ddr2_parameters.v* 3.00 JMK 04/22/05 Removed ODT off requirement during power down.* Added tAOND, tAOFD, tANPD, tAXPD, tAONPD, and tAOFPD parameters.* Added ODT status messages.* Updated the initialization sequence.* Disable ODT and CLK pins during self refresh.* Disable cmd and addr pins during power down and self refresh.****************************************************************************************/
// DO NOT CHANGE THE TIMESCALE
// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION
`timescale 1ps / 1ps
`define mod_name ddr2
module `mod_name ( CLK , CLK_N , CKE , CS_N , RAS_N , CAS_N , WE_N , DM_RDQS , BA , ADDR , DQ , DQS , DQS_N , RDQS_N , ODT );/****************************************************************************************** Disclaimer This software code and all associated documentation, comments or other * of Warranty: information (collectively "Software") is provided "AS IS" without * warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY * DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED * TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES * OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT * WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE * OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. * FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR * THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, * ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE * OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, * ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, * INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, * WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, * OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE * THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH * DAMAGES. Because some jurisdictions prohibit the exclusion or * limitation of liability for consequential or incidental damages, the * above limitation may not apply to you.** Copyright 2003 Micron Technology, Inc. All rights reserved.*****************************************************************************************/ // Timing parameters based on Speed Grade // SYMBOL UNITS DESCRIPTION // ------ ----- ----------- parameter tck = 3750; // tCK ps Nominal Clock Cycle Time parameter tck_min = 3750; // tCK ps Minimum Clock Cycle Time parameter tds = 100; // tDS ps DQ and DM input setup time relative to DQS parameter tdh = 225; // tDH ps DQ and DM input hold time relative to DQS parameter twpre = 0.25; // tWPRE tCK DQS Write Preamble parameter tis = 250; // tIS ps Input Setup Time parameter tih = 375; // tIH ps Input Hold Time parameter trc = 55000; // tRC ps Active to Active/Auto Refresh command time parameter trcd = 11250; // tRCD ps Active to Read/Write command time parameter trp = 11250; // tRP ps Precharge command period parameter twtr = 10000; // tWTR ps Write to Read command delay parameter cl_min = 3; // CL tCK Minimum CAS Latency // Mode Register parameter al_min = 0; // AL tCK Minimum Additive Latency parameter al_max = 5; // AL tCK Maximum Additive Latency parameter cl_max = 6; // CL tCK Maximum CAS Latency parameter wr_min = 2; // WR tCK Minimum Write Recovery parameter wr_max = 6; // WR tCK Maximum Write Recovery // Clock parameter tck_max = 8000; // tCK ps Maximum Clock Cycle Time parameter tch_min = 0.45; // tCH tCK Minimum Clock High-Level Pulse Width parameter tch_max = 0.55; // tCH tCK Maximum Clock High-Level Pulse Width parameter tcl_min = 0.45; // tCL tCK Minimum Clock Low-Level Pulse Width parameter tcl_max = 0.55; // tCL tCK Maximum Clock Low-Level Pulse Width // Data parameter tac_min = -500; // tAC ps DQ output access time from CK/CK# parameter tdipw = 0.35; // tDIPW tCK DQ and DM input Pulse Width // Data Strobe parameter tdqsh = 0.35; // tDQSH tCK DQS input High Pulse Width parameter tdqsl = 0.35; // tDQSL tCK DQS input Low Pulse Width parameter tdss = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) parameter tdsh = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) parameter twpst_min = 0.40; // tWPST tCK Minimum DQS Write Postamble parameter tdqss = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition // Command and Address parameter trpa = 15000+3000; // tRPA ps Precharge all command period parameter tipw = 0.6; // tIPW tCK Control and Address input Pulse Width parameter tccd = 2; // tCCD tCK Cas to Cas command delay parameter tras_min = 40000; // tRAS ps Minimum Active to Precharge command time parameter tras_max =70000000; // tRAS ps Maximum Active to Precharge command time parameter trtp = 7500; // tRTP ps Read to Precharge command delay parameter twr = 15000; // tWR ps Write recovery time parameter tmrd = 2; // tMRD tCK Load Mode Register command cycle time parameter tdllk = 200; // tDLLK tCK DLL locking time // Refresh parameter trfc_min = 105000; // tRFC ps Refresh to Refresh Command interval minimum value parameter trfc_max =70000000; // tRFC ps Refresh to Refresh Command Interval maximum value // Self Refresh parameter txsnr = 115000; // tXSNR ps Exit self refesh to a non-read command parameter txsrd = 200; // tXSRD tCK Exit self refresh to a read command parameter tisxr = 200; // tISXR ps CKE setup time during self refresh exit. // ODT parameter taond = 2; // tAONPD tCK ODT turn-on delay parameter taofd = 2.5; // tAONPD tCK ODT turn-off delay parameter taonpd = 1500; // tAONPD ps ODT turn-on (precharge power-down mode) parameter taofpd = 1500; // tAONPD ps ODT turn-off (precharge power-down mode) parameter tanpd = 3; // tANPD tCK ODT to power-down entry latency parameter taxpd = 8; // tAXPD tCk ODT power-down exit latency // Power Down parameter txard = 2; // tXARD tCK Exit active power down to a read command parameter txards = 6; // tXARDS tCK Exit low power active power down to a read command (set these to 6 tCk as in the spec (the model deletes the additive latency since that is programmable) parameter txp = 2; // tXP tCK Exit power down to a non-read command parameter tcke = 3; // tCKE tCK CKE minimum high or low pulse width // Size Parameters based on Part Width parameter DM_BITS = 2; // Set this parameter to control how many Data Mask bits are used parameter ADDR_BITS = 13; // MAX Address Bits parameter ROW_BITS = 14; // Set this parameter to control how many Address bits are used parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used **Same as part bit width** parameter DQS_BITS = 2; // Set this parameter to control how many Dqs bits are used parameter trrd = 7500; // tRRD Active bank a to Active bank b command time parameter tfaw = 37500; // tFAW Four access window time for the number of activates in an 8 bank device // Size Parameters parameter MODE_BITS = 18; // Set this parameter to control how many bits are in the mode register and extended mode register parameter BA_BITS = 2; // Set this parmaeter to control how many Bank Address bits are used parameter MAX_CMD_QUEUE = (6+5)*2; // This number represents the max number of clk edges that a command could be queued up for. parameter MEM_BITS = 10; // Set this parameter to control how many write data bursts can be stored in memory, can be 1 to 2^MEM_ADDRESS_BITS // Simulation parameters parameter no_halt = 0; // If set to 1, the model won't halt on command sequence/major errors parameter debug = 1; // Turn on Debug messages parameter bus_delay = 0; // delay in nanoseconds input CLK ;
input CLK_N ;
input CKE ;
input CS_N ;
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