📄 enc_16b20b.rpt
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Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
serial_data<12> .X...XXX....X......XXX.................. 8 8
serial_data<15> ............X.....XXXX.................. 5 5
serial_data<16> ............X....X.XXX.................. 5 5
serial_data<17> ............X...X..XXX.................. 5 5
serial_data<18> ............X..X...XXX.................. 5 5
serial_data<13> X....XXX...XX.X......................... 7 7
serial_data<10> X....XXX...XX.X......................... 7 7
N_PZ_1750 ...................XXXXX................ 5 5
serial_data<11> X......X....X........................... 3 3
serial_data<14> X.XXX...XX.XX........................... 8 8
serial_data<19> X.......X...X........................... 3 3
upper_enc/N166 .XXXX...XXX.XX......XX..XX.............. 13 13
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output (b) - Buried macrocell
*********************************** FB6 ***********************************
Number of signals used by logic mapping into function block: 18
Number of function block inputs used/remaining: 18/22
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 0/8
Number of PLA product terms used/remaining: 25/23
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
(unused) 0 FB6_1 (b)
upper_enc/dis_func/N174 13 FB6_2 4 (b)
frame_out_enc 1 FB6_3 5 I/O O
(unused) 0 FB6_4 6 I/O
(unused) 0 FB6_5 7 I/O
(unused) 0 FB6_6 8 I/O
(unused) 0 FB6_7 9 I/O
(unused) 0 FB6_8 (b)
(unused) 0 FB6_9 (b)
(unused) 0 FB6_10 (b)
(unused) 0 FB6_11 10 I/O
(unused) 0 FB6_12 (b)
N99 12 FB6_13 (b) (b)
(unused) 0 FB6_14 12 I/O
(unused) 0 FB6_15 13 I/O
(unused) 0 FB6_16 14 I/O
Signals Used by Logic in Function Block
1: N98 7: "data_trs<14>" 13: "lower_enc/prs_state_FFT2"
2: N_PZ_328 8: "data_trs<15>" 14: "upper_enc/N162"
3: "data_trs<10>" 9: "data_trs<8>" 15: "upper_enc/dis_func/N174"
4: "data_trs<11>" 10: "data_trs<9>" 16: "upper_enc/dis_func/prs_state_FFD1"
5: "data_trs<12>" 11: dis_in 17: "upper_enc/prs_state_FFT1"
6: "data_trs<13>" 12: "lower_enc/prs_state_FFT1"
18: "upper_enc/prs_state_FFT2"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
upper_enc/dis_func/N174
X.XXX...XX.....XXX...................... 9 9
frame_out_enc ...........XX...XX...................... 4 4
N99 XX...XXX..X..XX.XX...................... 10 10
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output (b) - Buried macrocell
*********************************** FB7 ***********************************
Number of signals used by logic mapping into function block: 0
Number of function block inputs used/remaining: 0/40
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 0/8
Number of PLA product terms used/remaining: 0/48
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
(unused) 0 FB7_1 (b)
(unused) 0 FB7_2 37 I/O
(unused) 0 FB7_3 36 I/O
(unused) 0 FB7_4 35 I/O
(unused) 0 FB7_5 33 I/O
(unused) 0 FB7_6 32 I/O
(unused) 0 FB7_7 31 I/O
(unused) 0 FB7_8 (b)
(unused) 0 FB7_9 (b)
(unused) 0 FB7_10 (b)
(unused) 0 FB7_11 30 I/O
(unused) 0 FB7_12 29 I/O
(unused) 0 FB7_13 28 I/O
(unused) 0 FB7_14 27 I/O
(unused) 0 FB7_15 (b)
(unused) 0 FB7_16 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output (b) - Buried macrocell
*********************************** FB8 ***********************************
Number of signals used by logic mapping into function block: 0
Number of function block inputs used/remaining: 0/40
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 0/8
Number of PLA product terms used/remaining: 0/48
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
(unused) 0 FB8_1 (b)
(unused) 0 FB8_2 15
(unused) 0 FB8_3 16 I/O
(unused) 0 FB8_4 17 I/O
(unused) 0 FB8_5 (b)
(unused) 0 FB8_6 19 I/O
(unused) 0 FB8_7 20 I/O
(unused) 0 FB8_8 (b)
(unused) 0 FB8_9 (b)
(unused) 0 FB8_10 (b)
(unused) 0 FB8_11 21 I/O
(unused) 0 FB8_12 22 I/O
(unused) 0 FB8_13 23 I/O
(unused) 0 FB8_14 24 I/O
(unused) 0 FB8_15 25 I/O
(unused) 0 FB8_16 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output (b) - Buried macrocell
;;-----------------------------------------------------------------;;
; Implemented Equations.
/dis_out := /"lower_enc/N160" * /"lower_enc/dis_func/N132"
+ "lower_enc/dis_func/prs_state_FFT3" * N_PZ_1737
+ /"lower_enc/dis_func/prs_state_FFT1" * N_PZ_1737
+ /"lower_enc/dis_func/prs_state_FFT2" * N_PZ_1737
+ /"lower_enc/N168" * N_PZ_330
+ /"lower_enc/N160" * /N99 * /"lower_enc/N168"
+ /"lower_enc/N160" * /N99 * N_PZ_330
+ /"lower_enc/dis_func/N132" * /N99 *
/"lower_enc/N168"
+ /"lower_enc/dis_func/N132" * /N99 * N_PZ_330
+ "lower_enc/N160" * "lower_enc/dis_func/N132" *
N99 * /"lower_enc/N168"
+ "lower_enc/N160" * "lower_enc/dis_func/N132" *
N99 * N_PZ_330
+ /"lower_enc/N160" * N99 * "lower_enc/N168" *
/N_PZ_330
+ /"lower_enc/dis_func/N132" * N99 *
"lower_enc/N168" * /N_PZ_330
+ "lower_enc/N160" * "lower_enc/dis_func/N132" *
/N99 * "lower_enc/N168" * /N_PZ_330
dis_out.CLKF = clk ;GCK
dis_out.CE = rst
dis_out.PRLD = Gnd
"lower_enc/N160" = /k_char * /"data_trs<4>"
+ /k_char * /"lower_enc/prs_state_FFT1" *
/"lower_enc/prs_state_FFT2"
+ /"lower_enc/dis_func/prs_state_FFT3" *
/"lower_enc/dis_func/prs_state_FFT1" * /"lower_enc/dis_func/prs_state_FFT2"
+ /k_char * "data_trs<3>" * /"data_trs<1>" *
/"data_trs<2>"
+ /k_char * /"data_trs<3>" * "data_trs<0>" *
/"data_trs<1>"
+ /k_char * /"data_trs<3>" * "data_trs<0>" *
/"data_trs<2>"
+ /k_char * /"data_trs<0>" * "data_trs<1>" *
/"data_trs<2>"
+ /k_char * /"data_trs<0>" * /"data_trs<1>" *
"data_trs<2>"
+ /k_char * /"data_trs<3>" * /"data_trs<0>" *
"data_trs<1>" * "data_trs<2>"
"lower_enc/dis_func/prs_state_FFT3".T := /"lower_enc/dis_func/prs_state_FFT3" *
"lower_enc/dis_func/prs_state_FFT1" * "lower_enc/dis_func/prs_state_FFT2"
+ "lower_enc/dis_func/prs_state_FFT3" *
/"lower_enc/dis_func/prs_state_FFT1" * /"lower_enc/dis_func/prs_state_FFT2" *
/"lower_enc/prs_state_FFT1"
+ "lower_enc/dis_func/prs_state_FFT3" *
/"lower_enc/dis_func/prs_state_FFT1" * /"lower_enc/dis_func/prs_state_FFT2" *
"lower_enc/prs_state_FFT2"
"lower_enc/dis_func/prs_state_FFT3".CLKF = clk ;GCK
/"lower_enc/dis_func/prs_state_FFT3".RSTF = rst
"lower_enc/dis_func/prs_state_FFT3".PRLD = Gnd
"lower_enc/dis_func/prs_state_FFT1".T := /"lower_enc/dis_func/prs_state_FFT3" *
"lower_enc/dis_func/prs_state_FFT1"
+ /"lower_enc/dis_func/prs_state_FFT3" * N98 *
"lower_enc/dis_func/prs_state_FFT2"
+ /"lower_enc/dis_func/prs_state_FFT3" *
/"lower_enc/dis_func/prs_state_FFT2" * "lower_enc/prs_state_FFT1" *
/"lower_enc/prs_state_FFT2"
"lower_enc/dis_func/prs_state_FFT1".CLKF = clk ;GCK
/"lower_enc/dis_func/prs_state_FFT1".RSTF = rst
"lower_enc/dis_func/prs_state_FFT1".PRLD = Gnd
N98 := "upper_enc/dis_func/prs_state_FFD1"
+ N98 * "upper_enc/prs_state_FFT1" *
/"upper_enc/prs_state_FFT2"
N98.CLKF = clk ;GCK
/N98.RSTF = rst
N98.PRLD = Gnd
"upper_enc/dis_func/prs_state_FFD1".T := N98 * "upper_enc/dis_func/prs_state_FFD1"
+ /N98 * /"upper_enc/dis_func/prs_state_FFD1" *
"upper_enc/prs_state_FFT1" * /"upper_enc/prs_state_FFT2"
"upper_enc/dis_func/prs_state_FFD1".CLKF = clk ;GCK
/"upper_enc/dis_func/prs_state_FFD1".RSTF = rst
"upper_enc/dis_func/prs_state_FFD1".PRLD = Gnd
"upper_enc/prs_state_FFT1".T := "upper_enc/prs_state_FFT1" * /frame_in_enc *
"upper_enc/prs_state_FFT2"
+ /"upper_enc/prs_state_FFT1" * frame_in_enc *
/"upper_enc/prs_state_FFT2"
"upper_enc/prs_state_FFT1".CLKF = clk ;GCK
/"upper_enc/prs_state_FFT1".RSTF = rst
"upper_enc/prs_state_FFT1".PRLD = Gnd
"upper_enc/prs_state_FFT2".T := "upper_enc/prs_state_FFT1" * /frame_in_enc *
"upper_enc/prs_state_FFT2"
+ "upper_enc/prs_state_FFT1" *
/"upper_enc/prs_state_FFT2" * /"upper_enc/enc_8b_10b/prs_state_FFT3" *
"upper_enc/enc_8b_10b/prs_state_FFT1" * "upper_enc/enc_8b_10b/prs_state_FFT2"
"upper_enc/prs_state_FFT2".CLKF = clk ;GCK
/"upper_enc/prs_state_FFT2".RSTF = rst
"upper_enc/prs_state_FFT2".PRLD = Gnd
"upper_enc/enc_8b_10b/prs_state_FFT3".T := /"upper_enc/enc_8b_10b/prs_state_FFT3" *
"upper_enc/enc_8b_10b/prs_state_FFT1" * "upper_enc/enc_8b_10b/prs_state_FFT2"
+ /"upper_enc/prs_state_FFT1" *
"upper_enc/enc_8b_10b/prs_state_FFT3" * /"upper_enc/enc_8b_10b/prs_state_FFT1" *
/"upper_enc/enc_8b_10b/prs_state_FFT2"
+ "upper_enc/prs_state_FFT2" *
"upper_enc/enc_8b_10b/prs_state_FFT3" * /"upper_enc/enc_8b_10b/prs_state_FFT1" *
/"upper_enc/enc_8b_10b/prs_state_FFT2"
"upper_enc/enc_8b_10b/prs_state_FFT3".CLKF = clk ;GCK
/"upper_enc/enc_8b_10b/prs_state_FFT3".RSTF = rst
"upper_enc/enc_8b_10b/prs_state_FFT3".PRLD = Gnd
"upper_enc/enc_8b_10b/prs_state_FFT1".T := /"upper_enc/enc_8b_10b/prs_state_FFT3" *
"upper_enc/enc_8b_10b/prs_state_FFT1"
+ "upper_enc/prs_state_FFT1" *
/"upper_enc/prs_state_FFT2" * /"upper_enc/enc_8b_10b/prs_state_FFT3" *
/"upper_enc/enc_8b_10b/prs_state_FFT2"
+ /"upper_enc/enc_8b_10b/prs_state_FFT3" *
/"upper_enc/s_func/prs_state_FFD1" * "upper_enc/s_func/prs_state_FFD2" *
"upper_enc/enc_8b_10b/prs_state_FFT2"
"upper_enc/enc_8b_10b/prs_state_FFT1".CLKF = clk ;GCK
/"upper_enc/enc_8b_10b/prs_state_FFT1".RSTF = rst
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