📄 enc_16b20b.rpt
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(unused) 0 FB2_2 76 I/O I
(unused) 0 FB2_3 77 I/O I
N_PZ_1780 4 FB2_4 78 I/O I
N_PZ_1744 3 FB2_5 79 I/O I
lower_enc/prs_state_FFT1 4 FB2_6 80 I/O I
lower_enc/s_func/prs_state_FFD1 4 FB2_7 81 I/O (b)
lower_enc/N164 19 FB2_8 (b) (b)
lower_enc/s_func/prs_state_FFD2 5 FB2_9 (b) (b)
lower_enc/enc_8b_10b/prs_state_FFT1
5 FB2_10 (b) (b)
lower_enc/enc_8b_10b/d_prel 6 FB2_11 83 I/O (b)
lower_enc/enc_8b_10b/b_prel 7 FB2_12 84 I/O (b)
lower_enc/enc_8b_10b/c_prel 6 FB2_13 85 I/O (b)
lower_enc/prs_state_FFT2 4 FB2_14 (b) (b)
lower_enc/enc_8b_10b/prs_state_FFT3
5 FB2_15 (b) (b)
lower_enc/enc_8b_10b/prs_state_FFT2
2 FB2_16 (b) (b)
Signals Used by Logic in Function Block
1: N99 8: frame_in_enc 15: "lower_enc/enc_8b_10b/prs_state_FFT2"
2: N_PZ_1780 9: "lower_enc/N160" 16: "lower_enc/enc_8b_10b/prs_state_FFT3"
3: "data_trs<0>" 10: "lower_enc/dis_func/N132"
17: "lower_enc/prs_state_FFT1"
4: "data_trs<1>" 11: "lower_enc/dis_func/prs_state_FFT1"
18: "lower_enc/prs_state_FFT2"
5: "data_trs<2>" 12: "lower_enc/dis_func/prs_state_FFT2"
19: "lower_enc/s_func/prs_state_FFD1"
6: "data_trs<3>" 13: "lower_enc/dis_func/prs_state_FFT3"
20: "lower_enc/s_func/prs_state_FFD2"
7: "data_trs<4>" 14: "lower_enc/enc_8b_10b/prs_state_FFT1"
21: rst
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
N_PZ_1780 ..XXXX.................................. 4 4
N_PZ_1744 .............XXXXX...................... 5 5
lower_enc/prs_state_FFT1
.......X........XX...................... 3 3
lower_enc/s_func/prs_state_FFD1
................XXXX.................... 4 4
lower_enc/N164 XXXXXXX.XX....XXXXXXX................... 16 16
lower_enc/s_func/prs_state_FFD2
..........XXXXXX..XX.................... 8 8
lower_enc/enc_8b_10b/prs_state_FFT1
.............XXXXXXX.................... 7 7
lower_enc/enc_8b_10b/d_prel
..XXXX.......XXXXX..X................... 10 10
lower_enc/enc_8b_10b/b_prel
..XXXX.......XXXXX..X................... 10 10
lower_enc/enc_8b_10b/c_prel
..XXXXX......XXXXX..X................... 11 11
lower_enc/prs_state_FFT2
.......X.....XXXXX...................... 6 6
lower_enc/enc_8b_10b/prs_state_FFT3
.............XXXXX...................... 5 5
lower_enc/enc_8b_10b/prs_state_FFT2
.............X.X........................ 2 2
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output (b) - Buried macrocell
*********************************** FB3 ***********************************
Number of signals used by logic mapping into function block: 25
Number of function block inputs used/remaining: 25/15
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 1/7
Number of PLA product terms used/remaining: 48/0
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
upper_enc/enc_8b_10b/d_prel 6 FB3_1 (b) (b)
upper_enc/enc_8b_10b/prs_state_FFT2
2 FB3_2 62 (b)
serial_data<4> 14 FB3_3 61 I/O O
(unused) 0 FB3_4 60 I/O I
upper_enc/enc_8b_10b/b_prel 7 FB3_5 (b) (b)
(unused) 0 FB3_6 58 I/O I
(unused) 0 FB3_7 57 I/O I
upper_enc/s_func/prs_state_FFD2 4 FB3_8 (b) (b)
upper_enc/enc_8b_10b/prs_state_FFT1
5 FB3_9 (b) (b)
upper_enc/prs_state_FFT2 4 FB3_10 (b) (b)
(unused) 0 FB3_11 56 I/O I
N_PZ_328 2 FB3_12 55 I/O I
upper_enc/prs_state_FFT1 4 FB3_13 54 I/O (b)
upper_enc/enc_8b_10b/c_prel 6 FB3_14 53 I/O (b)
upper_enc/enc_8b_10b/e_prel 14 FB3_15 52 I/O (b)
upper_enc/enc_8b_10b/prs_state_FFT3
5 FB3_16 (b) (b)
Signals Used by Logic in Function Block
1: N98 10: "data_trs<2>" 18: "upper_enc/dis_func/prs_state_FFD1"
2: N_PZ_1744 11: "data_trs<3>" 19: "upper_enc/enc_8b_10b/prs_state_FFT1"
3: N_PZ_1780 12: "data_trs<4>" 20: "upper_enc/enc_8b_10b/prs_state_FFT2"
4: N_PZ_328 13: "data_trs<8>" 21: "upper_enc/enc_8b_10b/prs_state_FFT3"
5: "data_trs<0>" 14: "data_trs<9>" 22: "upper_enc/prs_state_FFT1"
6: "data_trs<10>" 15: frame_in_enc 23: "upper_enc/prs_state_FFT2"
7: "data_trs<11>" 16: k_char 24: "upper_enc/s_func/prs_state_FFD1"
8: "data_trs<12>" 17: rst 25: "upper_enc/s_func/prs_state_FFD2"
9: "data_trs<1>"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
upper_enc/enc_8b_10b/d_prel
.....XX.....XX..X.XXXXX................. 10 10
upper_enc/enc_8b_10b/prs_state_FFT2
..................X.X................... 2 2
serial_data<4> .XX.X...XXXX...XX....................... 9 9
upper_enc/enc_8b_10b/b_prel
.....XX.....XX..X.XXXXX................. 10 10
upper_enc/s_func/prs_state_FFD2
X................XXXX..XX............... 7 7
upper_enc/enc_8b_10b/prs_state_FFT1
..................XXXXXXX............... 7 7
upper_enc/prs_state_FFT2
..............X...XXXXX................. 6 6
N_PZ_328 .....................XX................. 2 2
upper_enc/prs_state_FFT1
..............X......XX................. 3 3
upper_enc/enc_8b_10b/c_prel
...X.XXX....XX..X.XXX................... 10 10
upper_enc/enc_8b_10b/e_prel
.....XXX....XX..X.XXXXX................. 11 11
upper_enc/enc_8b_10b/prs_state_FFT3
..................XXXXX................. 5 5
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output (b) - Buried macrocell
*********************************** FB4 ***********************************
Number of signals used by logic mapping into function block: 37
Number of function block inputs used/remaining: 37/3
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 2/6
Number of PLA product terms used/remaining: 48/0
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
(unused) 0 FB4_1 (b)
dis_out 16 FB4_2 40 I/O O
serial_data<5> 2 FB4_3 41 I/O O
serial_data<6> 2 FB4_4 42 I/O O
serial_data<7> 2 FB4_5 44 I/O O
serial_data<8> 2 FB4_6 45 I/O O
serial_data<2> 5 FB4_7 46 I/O O
upper_enc/s_func/prs_state_FFD1 4 FB4_8 (b) (b)
upper_enc/N162 10 FB4_9 (b) (b)
upper_enc/dis_func/prs_state_FFD1 4 FB4_10 (b) (b)
serial_data<3> 5 FB4_11 47 I/O O
serial_data<0> 6 FB4_12 48 I/O O
serial_data<1> 2 FB4_13 49 I/O O
serial_data<9> 2 FB4_14 50 I/O O
N98 4 FB4_15 (b) (b)
N_PZ_1737 1 FB4_16 (b) (b)
Signals Used by Logic in Function Block
1: N98 14: "data_trs<9>" 26: "lower_enc/enc_8b_10b/e_prel"
2: N99 15: k_char 27: "lower_enc/enc_8b_10b/prs_state_FFT1"
3: N_PZ_1737 16: "lower_enc/N160" 28: "lower_enc/enc_8b_10b/prs_state_FFT2"
4: N_PZ_1744 17: "lower_enc/N164" 29: "lower_enc/enc_8b_10b/prs_state_FFT3"
5: N_PZ_330 18: "lower_enc/N168" 30: "lower_enc/prs_state_FFT1"
6: "data_trs<0>" 19: "lower_enc/dis_func/N132"
31: "lower_enc/prs_state_FFT2"
7: "data_trs<10>" 20: "lower_enc/dis_func/prs_state_FFT1"
32: rst
8: "data_trs<11>" 21: "lower_enc/dis_func/prs_state_FFT2"
33: "upper_enc/dis_func/prs_state_FFD1"
9: "data_trs<12>" 22: "lower_enc/dis_func/prs_state_FFT3"
34: "upper_enc/prs_state_FFT1"
10: "data_trs<5>" 23: "lower_enc/enc_8b_10b/b_prel"
35: "upper_enc/prs_state_FFT2"
11: "data_trs<6>" 24: "lower_enc/enc_8b_10b/c_prel"
36: "upper_enc/s_func/prs_state_FFD1"
12: "data_trs<7>" 25: "lower_enc/enc_8b_10b/d_prel"
37: "upper_enc/s_func/prs_state_FFD2"
13: "data_trs<8>"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
dis_out .XX.X..........X.XXXXX.........X........ 10 10
serial_data<5> .........................XXXX..X........ 5 5
serial_data<6> ........................X.XXX..X........ 5 5
serial_data<7> .......................X..XXX..X........ 5 5
serial_data<8> ......................X...XXX..X........ 5 5
serial_data<2> .........XXX..............XXXXXX........ 9 9
upper_enc/s_func/prs_state_FFD1
...............................X.XXXX... 5 5
upper_enc/N162 X.....XXX...XXX.................XXX..... 10 10
upper_enc/dis_func/prs_state_FFD1
X..............................XXXX..... 5 5
serial_data<3> ...X.....XXX..X.X..............X........ 7 7
serial_data<0> ...X.....XXX..X.X..............X........ 7 7
serial_data<1> ...X.......X...................X........ 3 3
serial_data<9> ...X.X.........................X........ 3 3
N98 X..............................XXXX..... 5 5
N_PZ_1737 ...................XXX.................. 3 3
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output (b) - Buried macrocell
*********************************** FB5 ***********************************
Number of signals used by logic mapping into function block: 26
Number of function block inputs used/remaining: 26/14
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 1/7
Number of PLA product terms used/remaining: 42/6
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
serial_data<12> 5 FB5_1 2 I/O O
serial_data<15> 2 FB5_2 1 I/O O
serial_data<16> 2 FB5_3 100 I/O O
serial_data<17> 2 FB5_4 99 I/O O
serial_data<18> 2 FB5_5 98 I/O O
serial_data<13> 5 FB5_6 97 I/O O
serial_data<10> 6 FB5_7 96 I/O O
(unused) 0 FB5_8 (b)
(unused) 0 FB5_9 (b)
(unused) 0 FB5_10 (b)
(unused) 0 FB5_11 (b)
N_PZ_1750 3 FB5_12 (b) (b)
serial_data<11> 2 FB5_13 94 I/O O
serial_data<14> 15 FB5_14 93 I/O O
serial_data<19> 2 FB5_15 92 I/O O
upper_enc/N166 11 FB5_16 (b) (b)
Signals Used by Logic in Function Block
1: N_PZ_1750 10: "data_trs<9>" 19: "upper_enc/enc_8b_10b/e_prel"
2: N_PZ_328 11: dis_in 20: "upper_enc/enc_8b_10b/prs_state_FFT1"
3: "data_trs<10>" 12: k_char 21: "upper_enc/enc_8b_10b/prs_state_FFT2"
4: "data_trs<11>" 13: rst 22: "upper_enc/enc_8b_10b/prs_state_FFT3"
5: "data_trs<12>" 14: "upper_enc/N162" 23: "upper_enc/prs_state_FFT1"
6: "data_trs<13>" 15: "upper_enc/N166" 24: "upper_enc/prs_state_FFT2"
7: "data_trs<14>" 16: "upper_enc/enc_8b_10b/b_prel"
25: "upper_enc/s_func/prs_state_FFD1"
8: "data_trs<15>" 17: "upper_enc/enc_8b_10b/c_prel"
26: "upper_enc/s_func/prs_state_FFD2"
9: "data_trs<8>" 18: "upper_enc/enc_8b_10b/d_prel"
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