📄 enc_16b20b.rpt
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cpldfit: version E.30 Xilinx Inc.
Fitter Report
Design Name: enc_16b20b Date: 11-12-2001, 9:30AM
Device Used: XCR3128XL-6-VQ100
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
63 /128 ( 49%) 259 /384 ( 67%) 50 /128 ( 39%) 43 /80 ( 53%) 146/320 ( 45%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 20 20 | I/O : 42 34
Output : 22 22 | GCK/IO : 1 3
Bidirectional : 0 0 |
GCK : 1 1 |
---- ----
Total 43 43
MACROCELL RESOURCES:
Total Macrocells Available 128
Registered Macrocells 50
Non-registered Macrocell driving I/O 1
GLOBAL RESOURCES:
Signal 'clk' mapped onto global clock net GCK1.
Universal Control Terms (Used/Available) : 4/0
BLOCK RESOURCES:
Total Function Block Local Control Terms (Used/Available) : 1/64
Total Foldback NANDs (Used/Available) : 0/64
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Slew Pin Pin Pin
Name Pt Used Rate # Type Use
N98 4 5 FB4_15 (b) (b)
N99 12 10 FB6_13 (b) (b)
N_PZ_1737 1 3 FB4_16 (b) (b)
N_PZ_1744 3 5 FB2_5 79 I/O I
N_PZ_1750 3 5 FB5_12 (b) (b)
N_PZ_1780 4 4 FB2_4 78 I/O I
N_PZ_328 2 2 FB3_12 55 I/O I
N_PZ_330 3 4 FB1_15 63 I/O I
dis_out 16 10 FB4_2 FAST 40 I/O O
frame_out_enc 1 4 FB6_3 FAST 5 I/O O
lower_enc/N160 10 11 FB1_8 (b) (b)
lower_enc/N164 19 16 FB2_8 (b) (b)
lower_enc/N168 6 8 FB1_10 (b) (b)
lower_enc/dis_func/N132
18 10 FB1_9 (b) (b)
lower_enc/dis_func/prs_state_FFT1
5 6 FB1_12 (b) (b)
lower_enc/dis_func/prs_state_FFT2
2 2 FB1_2 73 (b)
lower_enc/dis_func/prs_state_FFT3
5 5 FB1_16 (b) (b)
lower_enc/enc_8b_10b/b_prel
7 10 FB2_12 84 I/O (b)
lower_enc/enc_8b_10b/c_prel
6 11 FB2_13 85 I/O (b)
lower_enc/enc_8b_10b/d_prel
6 10 FB2_11 83 I/O (b)
lower_enc/enc_8b_10b/e_prel
14 11 FB1_1 (b) (b)
lower_enc/enc_8b_10b/prs_state_FFT1
5 7 FB2_10 (b) (b)
lower_enc/enc_8b_10b/prs_state_FFT2
2 2 FB2_16 (b) (b)
lower_enc/enc_8b_10b/prs_state_FFT3
5 5 FB2_15 (b) (b)
lower_enc/prs_state_FFT1
4 3 FB2_6 80 I/O I
lower_enc/prs_state_FFT2
4 6 FB2_14 (b) (b)
lower_enc/s_func/prs_state_FFD1
4 4 FB2_7 81 I/O (b)
lower_enc/s_func/prs_state_FFD2
5 8 FB2_9 (b) (b)
serial_data<0> 6 7 FB4_12 FAST 48 I/O O
serial_data<10> 6 7 FB5_7 FAST 96 I/O O
serial_data<11> 2 3 FB5_13 FAST 94 I/O O
serial_data<12> 5 8 FB5_1 FAST 2 I/O O
serial_data<13> 5 7 FB5_6 FAST 97 I/O O
serial_data<14> 15 8 FB5_14 FAST 93 I/O O
serial_data<15> 2 5 FB5_2 FAST 1 I/O O
serial_data<16> 2 5 FB5_3 FAST 100 I/O O
serial_data<17> 2 5 FB5_4 FAST 99 I/O O
serial_data<18> 2 5 FB5_5 FAST 98 I/O O
serial_data<19> 2 3 FB5_15 FAST 92 I/O O
serial_data<1> 2 3 FB4_13 FAST 49 I/O O
serial_data<2> 5 9 FB4_7 FAST 46 I/O O
serial_data<3> 5 7 FB4_11 FAST 47 I/O O
serial_data<4> 14 9 FB3_3 FAST 61 I/O O
serial_data<5> 2 5 FB4_3 FAST 41 I/O O
serial_data<6> 2 5 FB4_4 FAST 42 I/O O
serial_data<7> 2 5 FB4_5 FAST 44 I/O O
serial_data<8> 2 5 FB4_6 FAST 45 I/O O
serial_data<9> 2 3 FB4_14 FAST 50 I/O O
upper_enc/N162 10 10 FB4_9 (b) (b)
upper_enc/N166 11 13 FB5_16 (b) (b)
upper_enc/dis_func/N174
13 9 FB6_2 4 (b)
upper_enc/dis_func/prs_state_FFD1
4 5 FB4_10 (b) (b)
upper_enc/enc_8b_10b/b_prel
7 10 FB3_5 (b) (b)
upper_enc/enc_8b_10b/c_prel
6 10 FB3_14 53 I/O (b)
upper_enc/enc_8b_10b/d_prel
6 10 FB3_1 (b) (b)
upper_enc/enc_8b_10b/e_prel
14 11 FB3_15 52 I/O (b)
upper_enc/enc_8b_10b/prs_state_FFT1
5 7 FB3_9 (b) (b)
upper_enc/enc_8b_10b/prs_state_FFT2
2 2 FB3_2 62 (b)
upper_enc/enc_8b_10b/prs_state_FFT3
5 5 FB3_16 (b) (b)
upper_enc/prs_state_FFT1
4 3 FB3_13 54 I/O (b)
upper_enc/prs_state_FFT2
4 6 FB3_10 (b) (b)
upper_enc/s_func/prs_state_FFD1
4 5 FB4_8 (b) (b)
upper_enc/s_func/prs_state_FFD2
4 7 FB3_8 (b) (b)
** INPUTS **
Signal Loc Pin Pin Pin I/O
Name # Type Use Style
clk 90 GCK GCK
data_trs<0> FB1_3 72 I/O I
data_trs<10> FB2_1 75 I/O I
data_trs<11> FB2_2 76 I/O I
data_trs<12> FB2_3 77 I/O I
data_trs<13> FB1_13 65 I/O I
data_trs<14> FB1_14 64 I/O I
data_trs<15> FB1_15 63 I/O I
data_trs<1> FB1_4 71 I/O I
data_trs<2> FB1_5 70 I/O I
data_trs<3> FB1_6 69 I/O I
data_trs<4> FB1_7 68 I/O I
data_trs<5> FB3_4 60 I/O I
data_trs<6> FB3_6 58 I/O I
data_trs<7> FB3_7 57 I/O I
data_trs<8> FB2_4 78 I/O I
data_trs<9> FB2_5 79 I/O I
dis_in FB2_6 80 I/O I
frame_in_enc FB1_11 67 I/O I
k_char FB3_11 56 I/O I
rst FB3_12 55 I/O I
End of Resources Used by Successfully Mapped Logic
Legend: PU - Pull Up
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 8 19 19 48 0/0 9
FB2 13 21 21 48 0/0 10
FB3 12 25 25 48 1/0 9
FB4 15 37 37 48 10/0 10
FB5 12 26 26 42 10/0 10
FB6 3 18 18 25 1/0 9
FB7 0 0 0 0 0/0 10
FB8 0 0 0 0 0/0 9
---- ----- ----- -----
63 259 22/0 76
*********************************** FB1 ***********************************
Number of signals used by logic mapping into function block: 19
Number of function block inputs used/remaining: 19/21
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 1/7
Number of PLA product terms used/remaining: 48/0
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
lower_enc/enc_8b_10b/e_prel 14 FB1_1 (b) (b)
lower_enc/dis_func/prs_state_FFT2 2 FB1_2 73 (b)
(unused) 0 FB1_3 72 I/O I
(unused) 0 FB1_4 71 I/O I
(unused) 0 FB1_5 70 I/O I
(unused) 0 FB1_6 69 I/O I
(unused) 0 FB1_7 68 I/O I
lower_enc/N160 10 FB1_8 (b) (b)
lower_enc/dis_func/N132 18 FB1_9 (b) (b)
lower_enc/N168 6 FB1_10 (b) (b)
(unused) 0 FB1_11 67 I/O I
lower_enc/dis_func/prs_state_FFT1 5 FB1_12 (b) (b)
(unused) 0 FB1_13 65 I/O I
(unused) 0 FB1_14 64 I/O I
N_PZ_330 3 FB1_15 63 I/O I
lower_enc/dis_func/prs_state_FFT3 5 FB1_16 (b) (b)
Signals Used by Logic in Function Block
1: N98 8: "data_trs<6>" 14: "lower_enc/enc_8b_10b/prs_state_FFT1"
2: "data_trs<0>" 9: "data_trs<7>" 15: "lower_enc/enc_8b_10b/prs_state_FFT2"
3: "data_trs<1>" 10: k_char 16: "lower_enc/enc_8b_10b/prs_state_FFT3"
4: "data_trs<2>" 11: "lower_enc/dis_func/prs_state_FFT1"
17: "lower_enc/prs_state_FFT1"
5: "data_trs<3>" 12: "lower_enc/dis_func/prs_state_FFT2"
18: "lower_enc/prs_state_FFT2"
6: "data_trs<4>" 13: "lower_enc/dis_func/prs_state_FFT3"
19: rst
7: "data_trs<5>"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
lower_enc/enc_8b_10b/e_prel
.XXXXX.......XXXXXX..................... 11 11
lower_enc/dis_func/prs_state_FFT2
..........X.X........................... 2 2
lower_enc/N160 .XXXXX...XXXX...XX...................... 11 11
lower_enc/dis_func/N132
.XXXXX....XXX...XX...................... 10 10
lower_enc/N168 ......XXX.XXX...XX...................... 8 8
lower_enc/dis_func/prs_state_FFT1
X.........XXX...XX...................... 6 6
N_PZ_330 ......XX........XX...................... 4 4
lower_enc/dis_func/prs_state_FFT3
..........XXX...XX...................... 5 5
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output (b) - Buried macrocell
*********************************** FB2 ***********************************
Number of signals used by logic mapping into function block: 21
Number of function block inputs used/remaining: 21/19
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 1/7
Number of PLA product terms used/remaining: 48/0
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
(unused) 0 FB2_1 75 I/O I
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