main_tb_post.vhd

以太网16B/20B源代码包括编码器和解码器功能

-- **************************************************************
-- Owner:		Xilinx Inc.
-- File:  		main_tb_post.vhd
--
-- Purpose: 		Test for encoder and decoder functionality 
--			of 16 bit-wide transmission.
--
-- Author:		Jennifer Jenkins
-- Date:		3-31-2000
--	
-- ****************************************************************


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity MAIN_TB_POST is
end MAIN_TB_POST;


architecture BEHAVIOUR of MAIN_TB_POST is

-- ******************** CONSTANT DECLARATIONS ***********************
constant RESET_ACTIVE 			: STD_LOGIC := '0';

-- ********************* SIGNAL DECLARATIONS ************************
signal clk, rst				: STD_LOGIC;
signal data_trs, data_rcv 		: STD_LOGIC_VECTOR(15 downto 0);
signal k_char, dis_in, dis_out		: STD_LOGIC;
signal encoded_data, serial_data	: STD_LOGIC_VECTOR(19 downto 0);
signal frame_in_enc, frame_out_enc 	: STD_LOGIC;
signal frame_in_dec, frame_out_dec 	: STD_LOGIC;
signal char_err				: STD_LOGIC;


-- ******************** COMPONENT DECLARATION ***********************

-- 16B/20B Encoder Function
-- Encoder output VHDL timing model (time_sim_enc.vho)
component ENCODER_TIME_POST
	port(
		clk, data_trs_0, data_trs_1, data_trs_10, data_trs_11,
         	data_trs_12, data_trs_13, data_trs_14, data_trs_15, data_trs_2,
         	data_trs_3, data_trs_4, data_trs_5, data_trs_6, data_trs_7,
         	data_trs_8, data_trs_9, dis_in, frame_in_enc, 
		k_char, rst: in std_logic;
       	 	frame_out_enc: out std_logic;
        	dis_out, serial_data_0, serial_data_1, serial_data_10,
        	serial_data_11, serial_data_12, serial_data_13, serial_data_14,
        	serial_data_15, serial_data_16, serial_data_17, serial_data_18,
        	serial_data_19, serial_data_2, serial_data_3, serial_data_4,
        	serial_data_5, serial_data_6, serial_data_7, serial_data_8,
        	serial_data_9: inout std_logic);

end component;


-- 16B/20B Decoder Function
-- Decoder output VHDL timing model (time_sim_dec.vho)
component DECODER_TIME_POST
    port(
		clk, frame_in_dec, rst, serial_data_0, serial_data_1,
         	serial_data_10, serial_data_11, serial_data_12, serial_data_13,
         	serial_data_14, serial_data_15, serial_data_16, serial_data_17,
         	serial_data_18, serial_data_19, serial_data_2, serial_data_3,
         	serial_data_4, serial_data_5, serial_data_6, serial_data_7,
         	serial_data_8, serial_data_9: in std_logic;
         	decoded_data_0, decoded_data_1, decoded_data_10, decoded_data_11,
         	decoded_data_12, decoded_data_13, decoded_data_14,
         	decoded_data_15, decoded_data_2, decoded_data_3, decoded_data_4,
         	decoded_data_5, decoded_data_6, decoded_data_7, decoded_data_8,
         	decoded_data_9, frame_out_dec, ill_char_det: out std_logic);

end component;


-- 16B/20B Test Function Generator
component TST_16B20B_POST
	port(

		clk20		: inout	STD_LOGIC;			-- Local clock to encoder & decoder @ 20MHz	
		sync_reset	: out	STD_LOGIC;			-- Control signals to encoder
		data_trs	: out	STD_LOGIC_VECTOR (15 downto 0);	-- Date byte to encode
		k_char		: out 	STD_LOGIC;			-- Asserted denotes special 
									-- character transmission									
		disparity	: out	STD_LOGIC;			-- Denotes incoming parity
		run_dis		: in	STD_LOGIC;			-- Running disparity
		frame_to_enc	: inout	STD_LOGIC;			-- Control to start data encoding
		frame_out_enc	: in	STD_LOGIC;			-- Asserted - done with encoding
		data_rcv	: in	STD_LOGIC_VECTOR (15 downto 0);	-- Incoming data from decoder
		frame_in_dec	: out 	STD_LOGIC;			-- Control to start decoding
		frame_out_dec	: in	STD_LOGIC;			-- Asserted => done decoding
		data_from_enc	: in	STD_LOGIC_VECTOR (19 downto 0);	-- Data transfer from encoder
		data_to_dec	: out	STD_LOGIC_VECTOR (19 downto 0); -- Serial data to decoder
		ill_char_det	: in 	STD_LOGIC);			-- Asserted when illegal char detected	
		
end component;


begin

	-- ***************** COMPONENT ASSIGNMENTS *********************
	ENC: ENCODER_TIME_POST
		port map(
          		clk		=> clk,			
        		rst		=> rst,
			k_char		=> k_char,
	  		frame_in_enc 	=> frame_in_enc,	  
	  		dis_in		=> dis_in,			   	
	  		dis_out		=> dis_out,		  		
	  		frame_out_enc	=> frame_out_enc,
			data_trs_0	=> data_trs(0), 
			data_trs_1	=> data_trs(1), 
			data_trs_10	=> data_trs(10), 
			data_trs_11	=> data_trs(11),
         		data_trs_12	=> data_trs(12), 
			data_trs_13	=> data_trs(13), 
			data_trs_14	=> data_trs(14), 
			data_trs_15	=> data_trs(15), 
			data_trs_2	=> data_trs(2),
		        data_trs_3	=> data_trs(3), 
			data_trs_4	=> data_trs(4), 
			data_trs_5	=> data_trs(5), 
			data_trs_6	=> data_trs(6), 
			data_trs_7	=> data_trs(7),
 		        data_trs_8	=> data_trs(8), 
			data_trs_9	=> data_trs(9),  
        	        serial_data_0	=> encoded_data(0), 
			serial_data_1	=> encoded_data(1), 
			serial_data_10	=> encoded_data(10),
 		        serial_data_11	=> encoded_data(11), 
			serial_data_12	=> encoded_data(12), 
			serial_data_13	=> encoded_data(13), 
			serial_data_14	=> encoded_data(14),
		        serial_data_15	=> encoded_data(15), 
			serial_data_16	=> encoded_data(16), 
			serial_data_17	=> encoded_data(17), 
			serial_data_18	=> encoded_data(18),
		        serial_data_19	=> encoded_data(19), 
			serial_data_2	=> encoded_data(2), 
			serial_data_3	=> encoded_data(3), 
			serial_data_4	=> encoded_data(4),
		        serial_data_5	=> encoded_data(5), 
			serial_data_6	=> encoded_data(6), 
			serial_data_7	=> encoded_data(7), 
			serial_data_8	=> encoded_data(8),
		        serial_data_9	=> encoded_data(9));


	DEC: DECODER_TIME_POST	
		port map(	
			clk		=> clk,			
        		rst		=> rst,
 			frame_in_dec 	=> frame_in_dec,		  	 
	  		frame_out_dec	=> frame_out_dec,			  
	  		ill_char_det	=> char_err,
			serial_data_0	=> serial_data(0),
			serial_data_1	=> serial_data(1),
    		      	serial_data_10	=> serial_data(10),
			serial_data_11	=> serial_data(11), 
			serial_data_12	=> serial_data(12),
			serial_data_13	=> serial_data(13),
         		serial_data_14	=> serial_data(14), 
			serial_data_15	=> serial_data(15), 
			serial_data_16	=> serial_data(16), 
			serial_data_17	=> serial_data(17),
         		serial_data_18	=> serial_data(18), 
			serial_data_19	=> serial_data(19), 
			serial_data_2	=> serial_data(2), 
			serial_data_3	=> serial_data(3),
         		serial_data_4	=> serial_data(4), 
			serial_data_5	=> serial_data(5), 
			serial_data_6	=> serial_data(6),
			serial_data_7	=> serial_data(7),
      			serial_data_8	=> serial_data(8), 
			serial_data_9	=> serial_data(9),
         		decoded_data_0	=> data_rcv(0),
			decoded_data_1	=> data_rcv(1), 
			decoded_data_10	=> data_rcv(10), 
			decoded_data_11	=> data_rcv(11),
         		decoded_data_12	=> data_rcv(12), 
			decoded_data_13	=> data_rcv(13), 
			decoded_data_14	=> data_rcv(14),
         		decoded_data_15	=> data_rcv(15), 
			decoded_data_2	=> data_rcv(2), 
			decoded_data_3	=> data_rcv(3), 
			decoded_data_4	=> data_rcv(4),
         		decoded_data_5	=> data_rcv(5), 
			decoded_data_6	=> data_rcv(6), 
			decoded_data_7	=> data_rcv(7), 
			decoded_data_8	=> data_rcv(8),
         		decoded_data_9	=> data_rcv(9));
	

							
	TB: TST_16B20B_POST
		port map(
			clk20		=> clk,
			sync_reset	=> rst,		
			data_trs	=> data_trs,
			k_char		=> k_char,										
			disparity	=> dis_in,
			run_dis		=> dis_out,
			frame_to_enc	=> frame_in_enc,
			frame_out_enc	=> frame_out_enc,
			data_rcv	=> data_rcv,
			frame_in_dec	=> frame_in_dec,
			frame_out_dec	=> frame_out_dec,
			data_from_enc	=> encoded_data,
			data_to_dec	=> serial_data,
			ill_char_det	=> char_err);
  
   
end BEHAVIOUR;