📄 dec_16b20b.rpt
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(unused) 0 FB6_6 8 I/O
(unused) 0 FB6_7 9 I/O
(unused) 0 FB6_8 (b)
(unused) 0 FB6_9 (b)
upper_dec/N90 12 FB6_10 (b) (b)
(unused) 0 FB6_11 10 I/O
upper_dec/N86 12 FB6_12 (b) (b)
upper_dec/N82 13 FB6_13 (b) (b)
(unused) 0 FB6_14 12 I/O
(unused) 0 FB6_15 13 I/O
(unused) 0 FB6_16 14 I/O
Signals Used by Logic in Function Block
1: N_PZ_1626 7: "serial_data<14>" 12: "serial_data<19>"
2: rst 8: "serial_data<15>" 13: "upper_dec/dec_8b10b/prs_state_FFD1"
3: "serial_data<10>" 9: "serial_data<16>" 14: "upper_dec/dec_8b10b/prs_state_FFD2"
4: "serial_data<11>" 10: "serial_data<17>" 15: "upper_dec/prs_state_FFT1"
5: "serial_data<12>" 11: "serial_data<18>" 16: "upper_dec/prs_state_FFT2"
6: "serial_data<13>"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
upper_dec/N94 XX....XXXXXXXXXX........................ 12 12
upper_dec/N90 .XXXXXXXXX..XXXX........................ 13 13
upper_dec/N86 .XXXXXXXXX..XXXX........................ 13 13
upper_dec/N82 .XXXXXXXXX..XXXX........................ 13 13
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output (b) - Buried macrocell
*********************************** FB7 ***********************************
Number of signals used by logic mapping into function block: 13
Number of function block inputs used/remaining: 13/27
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 1/7
Number of PLA product terms used/remaining: 23/25
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
(unused) 0 FB7_1 (b)
(unused) 0 FB7_2 37 I/O I
(unused) 0 FB7_3 36 I/O I
(unused) 0 FB7_4 35 I/O I
(unused) 0 FB7_5 33 I/O I
(unused) 0 FB7_6 32 I/O I
(unused) 0 FB7_7 31 I/O I
(unused) 0 FB7_8 (b)
(unused) 0 FB7_9 (b)
(unused) 0 FB7_10 (b)
(unused) 0 FB7_11 30 I/O
(unused) 0 FB7_12 29 I/O
(unused) 0 FB7_13 28 I/O
(unused) 0 FB7_14 27 I/O
lower_dec/N90 12 FB7_15 (b) (b)
lower_dec/N86 12 FB7_16 (b) (b)
Signals Used by Logic in Function Block
1: "lower_dec/dec_8b10b/prs_state_FFD1"
6: "serial_data<0>" 10: "serial_data<4>"
2: "lower_dec/dec_8b10b/prs_state_FFD2"
7: "serial_data<1>" 11: "serial_data<5>"
3: "lower_dec/prs_state_FFT1"
8: "serial_data<2>" 12: "serial_data<6>"
4: "lower_dec/prs_state_FFT2"
9: "serial_data<3>" 13: "serial_data<7>"
5: rst
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
lower_dec/N90 XXXXXXXXXXXXX........................... 13 13
lower_dec/N86 XXXXXXXXXXXXX........................... 13 13
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output (b) - Buried macrocell
*********************************** FB8 ***********************************
Number of signals used by logic mapping into function block: 14
Number of function block inputs used/remaining: 14/26
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 0/8
Number of PLA product terms used/remaining: 28/20
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
(unused) 0 FB8_1 (b)
N99 29 FB8_2 15 (b)
(unused) 0 FB8_3 16 I/O
(unused) 0 FB8_4 17 I/O
(unused) 0 FB8_5 (b)
(unused) 0 FB8_6 19 I/O
(unused) 0 FB8_7 20 I/O
(unused) 0 FB8_8 (b)
(unused) 0 FB8_9 (b)
(unused) 0 FB8_10 (b)
(unused) 0 FB8_11 21 I/O
(unused) 0 FB8_12 22 I/O
(unused) 0 FB8_13 23 I/O
(unused) 0 FB8_14 24 I/O
(unused) 0 FB8_15 25 I/O
(unused) 0 FB8_16 (b)
Signals Used by Logic in Function Block
1: "lower_dec/err_chk/prs_state_FFD1"
6: "serial_data<1>" 11: "serial_data<6>"
2: "lower_dec/err_chk/prs_state_FFD2"
7: "serial_data<2>" 12: "serial_data<7>"
3: "lower_dec/prs_state_FFT1"
8: "serial_data<3>" 13: "serial_data<8>"
4: "lower_dec/prs_state_FFT2"
9: "serial_data<4>" 14: "serial_data<9>"
5: "serial_data<0>" 10: "serial_data<5>"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
N99 XXXXXXXXXXXXXX.......................... 14 14
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output (b) - Buried macrocell
;;-----------------------------------------------------------------;;
; Implemented Equations.
"decoded_data<0>" = "lower_dec/N82" * "lower_dec/prs_state_FFT1" *
"lower_dec/prs_state_FFT2"
"lower_dec/N82" := "serial_data<5>" * /"serial_data<0>" *
"serial_data<1>" * "lower_dec/dec_8b10b/prs_state_FFD2" *
"lower_dec/dec_8b10b/prs_state_FFD1" * "lower_dec/prs_state_FFT1" *
/"lower_dec/prs_state_FFT2"
+ /"serial_data<0>" * "serial_data<1>" *
"lower_dec/dec_8b10b/prs_state_FFD2" * "lower_dec/dec_8b10b/prs_state_FFD1" *
"lower_dec/prs_state_FFT1" * /"lower_dec/prs_state_FFT2" * "serial_data<4>"
+ /"serial_data<0>" * "serial_data<1>" *
"lower_dec/dec_8b10b/prs_state_FFD2" * "lower_dec/dec_8b10b/prs_state_FFD1" *
"lower_dec/prs_state_FFT1" * /"lower_dec/prs_state_FFT2" * "serial_data<6>"
+ /"serial_data<0>" * "serial_data<1>" *
"lower_dec/dec_8b10b/prs_state_FFD2" * "lower_dec/dec_8b10b/prs_state_FFD1" *
"lower_dec/prs_state_FFT1" * /"lower_dec/prs_state_FFT2" * "serial_data<7>"
+ "serial_data<0>" * "serial_data<1>" *
"lower_dec/dec_8b10b/prs_state_FFD2" * "lower_dec/dec_8b10b/prs_state_FFD1" *
"lower_dec/prs_state_FFT1" * /"lower_dec/prs_state_FFT2" * "serial_data<2>" *
/"serial_data<3>"
+ "serial_data<0>" * /"serial_data<1>" *
"lower_dec/dec_8b10b/prs_state_FFD2" * "lower_dec/dec_8b10b/prs_state_FFD1" *
"lower_dec/prs_state_FFT1" * /"lower_dec/prs_state_FFT2" * "serial_data<2>" *
"serial_data<3>"
+ "serial_data<0>" * /"serial_data<1>" *
"lower_dec/dec_8b10b/prs_state_FFD2" * "lower_dec/dec_8b10b/prs_state_FFD1" *
"lower_dec/prs_state_FFT1" * /"lower_dec/prs_state_FFT2" * /"serial_data<2>" *
/"serial_data<3>"
+ /"serial_data<0>" * "serial_data<1>" *
"lower_dec/dec_8b10b/prs_state_FFD2" * "lower_dec/dec_8b10b/prs_state_FFD1" *
"lower_dec/prs_state_FFT1" * /"lower_dec/prs_state_FFT2" * "serial_data<2>" *
"serial_data<3>"
+ /"serial_data<0>" * "serial_data<1>" *
"lower_dec/dec_8b10b/prs_state_FFD2" * "lower_dec/dec_8b10b/prs_state_FFD1" *
"lower_dec/prs_state_FFT1" * /"lower_dec/prs_state_FFT2" * /"serial_data<2>" *
/"serial_data<3>"
+ /"serial_data<0>" * /"serial_data<1>" *
"lower_dec/dec_8b10b/prs_state_FFD2" * "lower_dec/dec_8b10b/prs_state_FFD1" *
"lower_dec/prs_state_FFT1" * /"lower_dec/prs_state_FFT2" * /"serial_data<2>" *
"serial_data<3>"
+ /"serial_data<5>" * "serial_data<0>" *
/"serial_data<1>" * "lower_dec/dec_8b10b/prs_state_FFD2" *
"lower_dec/dec_8b10b/prs_state_FFD1" * "lower_dec/prs_state_FFT1" *
/"lower_dec/prs_state_FFT2" * /"serial_data<4>" * /"serial_data<6>" *
/"serial_data<7>"
"lower_dec/N82".CLKF = clk ;GCK
"lower_dec/N82".CE = rst
"lower_dec/N82".PRLD = Gnd
"lower_dec/dec_8b10b/prs_state_FFD2" := "lower_dec/dec_8b10b/prs_state_FFD1"
+ "lower_dec/dec_8b10b/prs_state_FFD2" *
"lower_dec/prs_state_FFT1" * /"lower_dec/prs_state_FFT2"
"lower_dec/dec_8b10b/prs_state_FFD2".CLKF = clk ;GCK
/"lower_dec/dec_8b10b/prs_state_FFD2".RSTF = rst
"lower_dec/dec_8b10b/prs_state_FFD2".PRLD = Gnd
"lower_dec/dec_8b10b/prs_state_FFD1".T := "lower_dec/dec_8b10b/prs_state_FFD2" *
"lower_dec/dec_8b10b/prs_state_FFD1"
+ /"lower_dec/dec_8b10b/prs_state_FFD2" *
/"lower_dec/dec_8b10b/prs_state_FFD1" * "lower_dec/prs_state_FFT1" *
/"lower_dec/prs_state_FFT2"
"lower_dec/dec_8b10b/prs_state_FFD1".CLKF = clk ;GCK
/"lower_dec/dec_8b10b/prs_state_FFD1".RSTF = rst
"lower_dec/dec_8b10b/prs_state_FFD1".PRLD = Gnd
"lower_dec/prs_state_FFT1".T := "lower_dec/prs_state_FFT1" * /frame_in_dec *
"lower_dec/prs_state_FFT2"
+ /"lower_dec/prs_state_FFT1" * frame_in_dec *
/"lower_dec/prs_state_FFT2"
"lower_dec/prs_state_FFT1".CLKF = clk ;GCK
/"lower_dec/prs_state_FFT1".RSTF = rst
"lower_dec/prs_state_FFT1".PRLD = Gnd
"lower_dec/prs_state_FFT2".T := "lower_dec/prs_state_FFT1" * /frame_in_dec *
"lower_dec/prs_state_FFT2"
+ "lower_dec/dec_8b10b/prs_state_FFD2" *
"lower_dec/dec_8b10b/prs_state_FFD1" * "lower_dec/prs_state_FFT1" *
/"lower_dec/prs_state_FFT2" * "lower_dec/err_chk/prs_state_FFD2" *
"lower_dec/err_chk/prs_state_FFD1"
"lower_dec/prs_state_FFT2".CLKF = clk ;GCK
/"lower_dec/prs_state_FFT2".RSTF = rst
"lower_dec/prs_state_FFT2".PRLD = Gnd
"lower_dec/err_chk/prs_state_FFD2" := "lower_dec/err_chk/prs_state_FFD1"
+ "lower_dec/prs_state_FFT1" *
/"lower_dec/prs_state_FFT2" * "lower_dec/err_chk/prs_state_FFD2"
"lower_dec/err_chk/prs_state_FFD2".CLKF = clk ;GCK
/"lower_dec/err_chk/prs_state_FFD2".RSTF = rst
"lower_dec/err_chk/prs_state_FFD2".PRLD = Gnd
"lower_dec/err_chk/prs_state_FFD1".T := "lower_dec/err_chk/prs_state_FFD2" *
"lower_dec/err_chk/prs_state_FFD1"
+ "lower_dec/prs_state_FFT1" *
/"lower_dec/prs_state_FFT2" * /"lower_dec/err_chk/prs_state_FFD2" *
/"lower_dec/err_chk/prs_state_FFD1"
"lower_dec/err_chk/prs_state_FFD1".CLKF = clk ;GCK
/"lower_dec/err_chk/prs_state_FFD1".RSTF = rst
"lower_dec/err_chk/prs_state_FFD1".PRLD = Gnd
"decoded_data<10>" = "upper_dec/N90" * "upper_dec/prs_state_FFT1" *
"upper_dec/prs_state_FFT2"
"upper_dec/N90" := "serial_data<13>"
Xor "serial_data<13>" *
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