📄 dec_16b20b.rpt
字号:
.........................XXXX........... 4 4
err/prs_state_FFD2
..................XX.......XX.....XX.... 6 6
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output (b) - Buried macrocell
*********************************** FB2 ***********************************
Number of signals used by logic mapping into function block: 20
Number of function block inputs used/remaining: 20/20
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 2/6
Number of PLA product terms used/remaining: 48/0
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
decoded_data<10> 1 FB2_1 75 I/O O
decoded_data<11> 1 FB2_2 76 I/O O
(unused) 0 FB2_3 77 I/O I
(unused) 0 FB2_4 78 I/O I
(unused) 0 FB2_5 79 I/O I
(unused) 0 FB2_6 80 I/O I
(unused) 0 FB2_7 81 I/O I
(unused) 0 FB2_8 (b)
N_PZ_1626 3 FB2_9 (b) (b)
upper_dec/N143 12 FB2_10 (b) (b)
(unused) 0 FB2_11 83 I/O I
(unused) 0 FB2_12 84 I/O I
(unused) 0 FB2_13 85 I/O I
N98 29 FB2_14 (b) (b)
upper_dec/err_chk/prs_state_FFD2 4 FB2_15 (b) (b)
upper_dec/err_chk/prs_state_FFD1 4 FB2_16 (b) (b)
Signals Used by Logic in Function Block
1: N_PZ_1626 8: "serial_data<15>" 15: "upper_dec/dec_8b10b/prs_state_FFD1"
2: rst 9: "serial_data<16>" 16: "upper_dec/dec_8b10b/prs_state_FFD2"
3: "serial_data<10>" 10: "serial_data<17>" 17: "upper_dec/err_chk/prs_state_FFD1"
4: "serial_data<11>" 11: "serial_data<18>" 18: "upper_dec/err_chk/prs_state_FFD2"
5: "serial_data<12>" 12: "serial_data<19>" 19: "upper_dec/prs_state_FFT1"
6: "serial_data<13>" 13: "upper_dec/N90" 20: "upper_dec/prs_state_FFT2"
7: "serial_data<14>" 14: "upper_dec/N94"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
decoded_data<10> ............X.....XX.................... 3 3
decoded_data<11> .............X....XX.................... 3 3
N_PZ_1626 ..........XX............................ 2 2
upper_dec/N143 XXXXX.XXXXXX..XX..XX.................... 15 15
N98 ..XXXXXXXXXX....XXXX.................... 14 14
upper_dec/err_chk/prs_state_FFD2
.X..............XXXX.................... 5 5
upper_dec/err_chk/prs_state_FFD1
.X..............XXXX.................... 5 5
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output (b) - Buried macrocell
*********************************** FB3 ***********************************
Number of signals used by logic mapping into function block: 21
Number of function block inputs used/remaining: 21/19
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 1/7
Number of PLA product terms used/remaining: 48/0
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
(unused) 0 FB3_1 (b)
lower_dec/N106 12 FB3_2 62 (b)
decoded_data<12> 1 FB3_3 61 I/O O
decoded_data<13> 1 FB3_4 60 I/O O
(unused) 0 FB3_5 (b)
decoded_data<14> 1 FB3_6 58 I/O O
decoded_data<15> 1 FB3_7 57 I/O O
(unused) 0 FB3_8 (b)
lower_dec/N102 14 FB3_9 (b) (b)
lower_dec/N110 12 FB3_10 (b) (b)
decoded_data<8> 1 FB3_11 56 I/O O
decoded_data<9> 1 FB3_12 55 I/O O
decoded_data<1> 1 FB3_13 54 I/O O
decoded_data<2> 1 FB3_14 53 I/O O
(unused) 0 FB3_15 52 I/O I
lower_dec/N98 15 FB3_16 (b) (b)
Signals Used by Logic in Function Block
1: "lower_dec/N86" 8: "serial_data<4>" 15: "upper_dec/N106"
2: "lower_dec/N90" 9: "serial_data<5>" 16: "upper_dec/N110"
3: "lower_dec/dec_8b10b/prs_state_FFD1"
10: "serial_data<6>" 17: "upper_dec/N82"
4: "lower_dec/dec_8b10b/prs_state_FFD2"
11: "serial_data<7>" 18: "upper_dec/N86"
5: "lower_dec/prs_state_FFT1"
12: "serial_data<8>" 19: "upper_dec/N98"
6: "lower_dec/prs_state_FFT2"
13: "serial_data<9>" 20: "upper_dec/prs_state_FFT1"
7: rst 14: "upper_dec/N102" 21: "upper_dec/prs_state_FFT2"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
lower_dec/N106 ..XXXXXXXXXXX........................... 11 11
decoded_data<12> ..................XXX................... 3 3
decoded_data<13> .............X.....XX................... 3 3
decoded_data<14> ..............X....XX................... 3 3
decoded_data<15> ...............X...XX................... 3 3
lower_dec/N102 ..XXXXXXXXXXX........................... 11 11
lower_dec/N110 ..XXXXXXXXXXX........................... 11 11
decoded_data<8> ................X..XX................... 3 3
decoded_data<9> .................X.XX................... 3 3
decoded_data<1> X...XX.................................. 3 3
decoded_data<2> .X..XX.................................. 3 3
lower_dec/N98 ..XXXXXXXXXXX........................... 11 11
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output (b) - Buried macrocell
*********************************** FB4 ***********************************
Number of signals used by logic mapping into function block: 20
Number of function block inputs used/remaining: 20/20
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 1/7
Number of PLA product terms used/remaining: 45/3
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
(unused) 0 FB4_1 (b)
decoded_data<3> 1 FB4_2 40 I/O O
decoded_data<4> 1 FB4_3 41 I/O O
decoded_data<5> 1 FB4_4 42 I/O O
decoded_data<6> 1 FB4_5 44 I/O O
decoded_data<7> 1 FB4_6 45 I/O O
(unused) 0 FB4_7 46 I/O I
(unused) 0 FB4_8 (b)
(unused) 0 FB4_9 (b)
lower_dec/N82 13 FB4_10 (b) (b)
(unused) 0 FB4_11 47 I/O I
(unused) 0 FB4_12 48 I/O I
(unused) 0 FB4_13 49 I/O
(unused) 0 FB4_14 50 I/O
lower_dec/N143 14 FB4_15 (b) (b)
lower_dec/N94 18 FB4_16 (b) (b)
Signals Used by Logic in Function Block
1: "lower_dec/N102" 8: "lower_dec/prs_state_FFT1"
15: "serial_data<4>"
2: "lower_dec/N106" 9: "lower_dec/prs_state_FFT2"
16: "serial_data<5>"
3: "lower_dec/N110" 10: rst 17: "serial_data<6>"
4: "lower_dec/N94" 11: "serial_data<0>" 18: "serial_data<7>"
5: "lower_dec/N98" 12: "serial_data<1>" 19: "serial_data<8>"
6: "lower_dec/dec_8b10b/prs_state_FFD1"
13: "serial_data<2>" 20: "serial_data<9>"
7: "lower_dec/dec_8b10b/prs_state_FFD2"
14: "serial_data<3>"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
decoded_data<3> ...X...XX............................... 3 3
decoded_data<4> ....X..XX............................... 3 3
decoded_data<5> X......XX............................... 3 3
decoded_data<6> .X.....XX............................... 3 3
decoded_data<7> ..X....XX............................... 3 3
lower_dec/N82 .....XXXXXXXXXXXXX...................... 13 13
lower_dec/N143 .....XXXXXXXX.XXXXXX.................... 14 14
lower_dec/N94 .....XXXXX....XXXXXX.................... 11 11
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output (b) - Buried macrocell
*********************************** FB5 ***********************************
Number of signals used by logic mapping into function block: 12
Number of function block inputs used/remaining: 12/28
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 1/7
Number of PLA product terms used/remaining: 39/9
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
(unused) 0 FB5_1 2 I/O I
(unused) 0 FB5_2 1 I/O
(unused) 0 FB5_3 100 I/O
(unused) 0 FB5_4 99 I/O
(unused) 0 FB5_5 98 I/O
(unused) 0 FB5_6 97 I/O
(unused) 0 FB5_7 96 I/O
(unused) 0 FB5_8 (b)
(unused) 0 FB5_9 (b)
upper_dec/N102 13 FB5_10 (b) (b)
upper_dec/N110 12 FB5_11 (b) (b)
upper_dec/N98 13 FB5_12 (b) (b)
(unused) 0 FB5_13 94 I/O
(unused) 0 FB5_14 93 I/O
(unused) 0 FB5_15 92 I/O
upper_dec/N106 12 FB5_16 (b) (b)
Signals Used by Logic in Function Block
1: N_PZ_1626 5: "serial_data<16>" 9: "upper_dec/dec_8b10b/prs_state_FFD1"
2: rst 6: "serial_data<17>" 10: "upper_dec/dec_8b10b/prs_state_FFD2"
3: "serial_data<14>" 7: "serial_data<18>" 11: "upper_dec/prs_state_FFT1"
4: "serial_data<15>" 8: "serial_data<19>" 12: "upper_dec/prs_state_FFT2"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
upper_dec/N102 XXXXXXXXXXXX............................ 12 12
upper_dec/N110 XXXXXXXXXXXX............................ 12 12
upper_dec/N98 XXXXXXXXXXXX............................ 12 12
upper_dec/N106 .XXXXXXXXXXX............................ 11 11
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output (b) - Buried macrocell
*********************************** FB6 ***********************************
Number of signals used by logic mapping into function block: 16
Number of function block inputs used/remaining: 16/24
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 1/7
Number of PLA product terms used/remaining: 46/2
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
(unused) 0 FB6_1 (b)
upper_dec/N94 14 FB6_2 4 (b)
(unused) 0 FB6_3 5 I/O I
(unused) 0 FB6_4 6 I/O
(unused) 0 FB6_5 7 I/O
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -