shiweichefa.rpt

maxplus做的四位乘法器

         # !M1 &  M2 &  M4 &  N1 &  N3
         #  M1 &  M3 & !N1 &  N2 &  N4
         # !M1 &  M2 & !M4 &  N1 & !N3;

-- Node name is '|7weijiafai:1|quanjiaqi:4|7486:1|~4~4' = '|7weijiafai:1|quanjiaqi:4|7486:1|1~4' 
-- Equation name is '_LC045', type is buried 
-- synthesized logic cell 
_LC045   = LCELL( _EQ018 $  GND);
  _EQ018 =  M1 & !M3 & !N1 &  N2 & !N4
         # !M1 & !M2 & !M4 & !N2
         # !M1 & !M2 & !M3 & !M4
         # !M1 & !M2 & !M3 & !N1
         # !M1 & !M2 & !N1 & !N2;

-- Node name is '|7weijiafai:1|quanjiaqi:4|7486:1|~4~5' = '|7weijiafai:1|quanjiaqi:4|7486:1|1~5' 
-- Equation name is '_LC055', type is buried 
-- synthesized logic cell 
_LC055   = LCELL( _EQ019 $  GND);
  _EQ019 = !M1 & !N1 & !N2 & !N3
         # !M1 & !M3 & !N1 & !N3
         # !M2 & !M3 & !M4 & !N4
         # !M2 & !N1 & !N2 & !N4
         # !N1 & !N2 & !N3 & !N4;

-- Node name is '|7weijiafai:1|quanjiaqi:5|7486:1|~4~1' = '|7weijiafai:1|quanjiaqi:5|7486:1|1~1' 
-- Equation name is '_LC053', type is buried 
-- synthesized logic cell 
_LC053   = LCELL( _EQ020 $  GND);
  _EQ020 =  M1 &  M2 & !M3 &  M4 &  N1 &  N2 & !N3 &  N4
         #  M1 &  M2 & !M4 &  N1 &  N2 &  N3 & !N4
         #  M1 &  M2 & !M3 & !M4 &  N2 &  N3 & !N4
         #  M2 &  M3 & !M4 &  N1 &  N2 & !N3 & !N4
         #  M1 & !M2 & !M3 &  M4 &  N1 & !N2 &  N4;

-- Node name is '|7weijiafai:1|quanjiaqi:5|7486:1|~4~2' = '|7weijiafai:1|quanjiaqi:5|7486:1|1~2' 
-- Equation name is '_LC052', type is buried 
-- synthesized logic cell 
_LC052   = LCELL( _EQ021 $  GND);
  _EQ021 =  M1 & !M2 &  M4 &  N1 & !N2 & !N3 &  N4
         # !M1 &  M3 &  M4 &  N1 &  N3 &  N4
         # !M1 &  M2 &  N1 &  N2 &  N3 &  N4
         #  M1 &  M2 &  M3 &  M4 & !N1 &  N4
         # !M1 &  M2 &  M3 &  M4 &  N1 &  N4;

-- Node name is '|7weijiafai:1|quanjiaqi:5|7486:1|~4~3' = '|7weijiafai:1|quanjiaqi:5|7486:1|1~3' 
-- Equation name is '_LC051', type is buried 
-- synthesized logic cell 
_LC051   = LCELL( _EQ022 $  GND);
  _EQ022 =  M1 &  M4 & !N1 &  N2 &  N3 &  N4
         #  M1 &  M2 &  M3 & !M4 & !N2 &  N4
         #  M2 &  M3 &  M4 & !N1 &  N3 & !N4
         # !M2 &  M4 &  N1 &  N2 &  N3 & !N4
         # !M1 &  M2 & !M4 & !N1 &  N2 &  N4;

-- Node name is '|7weijiafai:1|quanjiaqi:5|7486:1|~4~4' = '|7weijiafai:1|quanjiaqi:5|7486:1|1~4' 
-- Equation name is '_LC050', type is buried 
-- synthesized logic cell 
_LC050   = LCELL( _EQ023 $  GND);
  _EQ023 = !M1 & !M3 &  M4 & !N1 &  N2 & !N4
         # !M1 & !M3 &  M4 &  N2 & !N3 & !N4
         # !M1 &  M3 & !M4 & !N2 &  N3 & !N4
         # !M2 &  M3 & !M4 & !N2 &  N3 & !N4
         # !M2 &  M3 & !M4 & !N1 &  N3 & !N4;

-- Node name is '|7weijiafai:1|quanjiaqi:5|7486:1|~4~5' = '|7weijiafai:1|quanjiaqi:5|7486:1|1~5' 
-- Equation name is '_LC049', type is buried 
-- synthesized logic cell 
_LC049   = LCELL( _EQ024 $  GND);
  _EQ024 = !M1 & !M2 &  M4 & !N1 &  N2 & !N3
         # !M1 &  M2 & !M3 & !N1 & !N2 &  N4
         #  M2 & !M3 & !M4 & !N1 & !N3 &  N4
         #  M1 &  M3 & !N1 & !N2 &  N3
         # !M1 &  M2 & !M3 & !M4 &  N4;

-- Node name is '|7weijiafai:1|quanjiaqi:5|7486:1|~4~6' = '|7weijiafai:1|quanjiaqi:5|7486:1|1~6' 
-- Equation name is '_LC057', type is buried 
-- synthesized logic cell 
_LC057   = LCELL( _EQ025 $  GND);
  _EQ025 = !M1 & !M2 &  M3 & !N2 &  N3
         # !M1 & !M2 &  M3 & !M4 &  N3
         #  M4 & !N1 &  N2 & !N3 & !N4
         # !M2 & !M3 &  M4 & !N1 &  N2
         # !M1 & !M2 & !M3 &  M4 &  N2;

-- Node name is '|7weijiafai:1|quanjiaqi:5|7486:1|~4~7' = '|7weijiafai:1|quanjiaqi:5|7486:1|1~7' 
-- Equation name is '_LC059', type is buried 
-- synthesized logic cell 
_LC059   = LCELL( _EQ026 $  GND);
  _EQ026 = !M2 & !M3 &  M4 &  N2 & !N4
         #  M2 & !M4 & !N2 & !N3 &  N4
         #  M2 & !N1 & !N2 & !N3 &  N4
         # !M1 &  M2 & !N2 & !N3 &  N4;

-- Node name is '|7weijiafai:1|quanjiaqi:6|~3~2' = '|7weijiafai:1|quanjiaqi:6|CN~2' 
-- Equation name is '_LC042', type is buried 
-- synthesized logic cell 
_LC042   = LCELL( _EQ027 $  GND);
  _EQ027 =  M1 &  M2 & !M3 &  N2
         # !M1 & !M2 &  N2 &  N3
         # !M1 & !M2 & !N1 &  N2
         # !M1 & !M3 & !N1 & !N2
         # !M2 & !M4 & !N1 & !N2;

-- Node name is '|7weijiafai:1|quanjiaqi:6|~3~3' = '|7weijiafai:1|quanjiaqi:6|CN~3' 
-- Equation name is '_LC043', type is buried 
-- synthesized logic cell 
_LC043   = LCELL( _EQ028 $  GND);
  _EQ028 = !M1 & !M4 & !N1 & !N3
         # !M2 & !M3 & !N2
         # !M2 & !N2 & !N3
         # !M2 & !M4 & !N3
         # !M1 & !M2 & !M4;

-- Node name is '|7weijiafai:1|quanjiaqi:6|~3~4' = '|7weijiafai:1|quanjiaqi:6|CN~4' 
-- Equation name is '_LC026', type is buried 
-- synthesized logic cell 
_LC026   = LCELL( _EQ029 $  GND);
  _EQ029 = !M4 & !N2 & !N3
         # !M3 & !N3
         # !M3 & !M4;

-- Node name is '|7weijiafai:1|quanjiaqi:6|~3~1' 
-- Equation name is '_LC036', type is buried 
-- synthesized logic cell 
_LC036   = LCELL( _EQ030 $  _EQ031);
  _EQ030 = !_LC026 & !_LC042 & !_LC043 & !M1 &  M2 &  M3 &  M4 &  N1 & !N2 & 
              N4 &  _X001
         # !_LC026 & !_LC042 & !_LC043 & !M2 &  M4 & !N1 &  N2 &  N3 &  N4 & 
              _X001
         # !_LC026 & !_LC042 & !_LC043 &  M1 & !M2 &  M4 &  N1 & !N2 &  N4 & 
              _X001
         # !_LC026 & !_LC042 & !_LC043 &  M2 & !M3 &  N1 &  N2 &  N4 &  _X001;
  _X001  = EXP(!N1 & !N2 & !N3);
  _EQ031 = !_LC026 & !_LC042 & !_LC043 &  N4 &  _X001;
  _X001  = EXP(!N1 & !N2 & !N3);

-- Node name is '|7weijiafai:1|quanjiaqi:6|7486:1|~4~1' = '|7weijiafai:1|quanjiaqi:6|7486:1|1~1' 
-- Equation name is '_LC061', type is buried 
-- synthesized logic cell 
_LC061   = LCELL( _EQ032 $  GND);
  _EQ032 =  M1 &  M2 & !M3 &  M4 &  N1 & !N3 &  N4
         #  M1 & !M2 &  M3 &  M4 &  N1 & !N2 &  N4
         #  M1 & !M3 &  M4 &  N1 &  N2 & !N3 &  N4
         #  M1 &  M3 & !M4 &  N1 &  N2 &  N3 & !N4
         #  M1 &  M2 &  M3 & !M4 &  N1 &  N3 & !N4;

-- Node name is '|7weijiafai:1|quanjiaqi:6|7486:1|~4~2' = '|7weijiafai:1|quanjiaqi:6|7486:1|1~2' 
-- Equation name is '_LC054', type is buried 
-- synthesized logic cell 
_LC054   = LCELL( _EQ033 $  GND);
  _EQ033 =  M1 &  M2 &  M4 &  N1 &  N2 &  N4
         #  M1 &  M2 &  M4 &  N1 &  N2 & !N3
         #  M2 &  M3 &  N1 &  N2 &  N3 & !N4
         #  M1 &  M2 & !M3 &  N1 &  N2 &  N4
         #  M1 &  M2 &  M3 & !M4 &  N2 &  N3;

-- Node name is '|7weijiafai:1|quanjiaqi:6|7486:1|~4~3' = '|7weijiafai:1|quanjiaqi:6|7486:1|1~3' 
-- Equation name is '_LC058', type is buried 
-- synthesized logic cell 
_LC058   = LCELL( _EQ034 $  GND);
  _EQ034 =  M1 &  M2 & !M3 & !M4 &  N3 &  N4
         # !M1 &  M2 &  M3 &  M4 & !N2 &  N4
         #  M2 &  M3 &  M4 & !N1 & !N2 &  N4
         #  M2 & !M3 &  M4 &  N2 & !N3 &  N4
         #  M2 &  M3 & !M4 &  N2 &  N3 & !N4;

-- Node name is '|7weijiafai:1|quanjiaqi:6|7486:1|~4~4' = '|7weijiafai:1|quanjiaqi:6|7486:1|1~4' 
-- Equation name is '_LC060', type is buried 
-- synthesized logic cell 
_LC060   = LCELL( _EQ035 $  GND);
  _EQ035 =  M3 &  M4 &  N1 &  N2 & !N3 & !N4
         # !M2 &  M4 & !N1 &  N2 &  N3 &  N4
         # !M1 & !M2 &  M4 &  N2 &  N3 &  N4
         # !M1 &  M2 &  M4 & !N1 & !N2 &  N3
         # !M1 & !M2 &  M3 & !N1 & !N3 &  N4;

-- Node name is '|7weijiafai:1|quanjiaqi:6|7486:1|~4~5' = '|7weijiafai:1|quanjiaqi:6|7486:1|1~5' 
-- Equation name is '_LC034', type is buried 
-- synthesized logic cell 
_LC034   = LCELL( _EQ036 $  GND);
  _EQ036 = !M1 & !M2 &  M4 & !N2 &  N3 & !N4
         # !M1 & !M3 &  M4 & !N1 &  N3 & !N4
         # !M2 &  M3 & !M4 & !N1 & !N2 &  N4
         # !M1 &  M3 & !M4 & !N1 & !N3 &  N4
         # !M1 & !M2 &  M3 & !M4 &  N4;

-- Node name is '|7weijiafai:1|quanjiaqi:6|7486:1|~4~6' = '|7weijiafai:1|quanjiaqi:6|7486:1|1~6' 
-- Equation name is '_LC038', type is buried 
-- synthesized logic cell 
_LC038   = LCELL( _EQ037 $  GND);
  _EQ037 =  M4 & !N1 & !N2 &  N3 & !N4
         # !M2 & !M3 &  M4 & !N2 &  N3
         # !M2 & !M3 &  M4 &  N3 & !N4
         # !M3 &  M4 & !N2 &  N3 & !N4
         # !M2 &  M3 & !M4 & !N3 &  N4;



--     Shareable expanders that are duplicated in multiple LABs:
--    _X002 occurs in LABs C, D
--    _X004 occurs in LABs C, D




Project Information                          f:\shiweichenfaqi\shiweichefa.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,501K