📄 shiweichefa.rpt
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r = Fitter-inserted logic cell
Device-Specific Information: f:\shiweichenfaqi\shiweichefa.rpt
shiweichefa
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+--- LC17 P6
| +- LC26 |7weijiafai:1|quanjiaqi:6|CN~4
| |
| | Other LABs fed by signals
| | that feed LAB 'B'
LC | | | A B C D | Logic cells that feed LAB 'B':
Pin
11 -> * - | - * * * | <-- M2
9 -> * * | - * * * | <-- M3
8 -> * * | - * * * | <-- M4
12 -> * * | - * * * | <-- N2
6 -> * * | - * * * | <-- N3
20 -> * - | - * * * | <-- N4
LC61 -> * - | - * - - | <-- |7weijiafai:1|quanjiaqi:6|7486:1|1~1
LC54 -> * - | - * - - | <-- |7weijiafai:1|quanjiaqi:6|7486:1|1~2
LC58 -> * - | - * - - | <-- |7weijiafai:1|quanjiaqi:6|7486:1|1~3
LC60 -> * - | - * - - | <-- |7weijiafai:1|quanjiaqi:6|7486:1|1~4
LC34 -> * - | - * - - | <-- |7weijiafai:1|quanjiaqi:6|7486:1|1~5
LC38 -> * - | - * - - | <-- |7weijiafai:1|quanjiaqi:6|7486:1|1~6
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\shiweichenfaqi\shiweichefa.rpt
shiweichefa
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------------------------- LC37 P1
| +----------------------------- LC40 P2
| | +--------------------------- LC41 P3
| | | +------------------------- LC46 P4
| | | | +----------------------- LC48 P7
| | | | | +--------------------- LC33 P8
| | | | | | +------------------- LC44 |6weijiafai:2|quanjiaqi:6|~2~1
| | | | | | | +----------------- LC47 |6weijiafai:2|quanjiaqi:6|~7~1
| | | | | | | | +--------------- LC39 |6weijiafai:2|quanjiaqi:6|~8~1
| | | | | | | | | +------------- LC35 |7weijiafai:1|quanjiaqi:3|7486:1|1~1
| | | | | | | | | | +----------- LC45 |7weijiafai:1|quanjiaqi:4|7486:1|1~4
| | | | | | | | | | | +--------- LC36 |7weijiafai:1|quanjiaqi:6|~3~1
| | | | | | | | | | | | +------- LC42 |7weijiafai:1|quanjiaqi:6|CN~2
| | | | | | | | | | | | | +----- LC43 |7weijiafai:1|quanjiaqi:6|CN~3
| | | | | | | | | | | | | | +--- LC34 |7weijiafai:1|quanjiaqi:6|7486:1|1~5
| | | | | | | | | | | | | | | +- LC38 |7weijiafai:1|quanjiaqi:6|7486:1|1~6
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC44 -> - - - - * * - - - - - - - - - - | - - * - | <-- |6weijiafai:2|quanjiaqi:6|~2~1
LC47 -> - - - - * * - - - - - - - - - - | - - * - | <-- |6weijiafai:2|quanjiaqi:6|~7~1
LC39 -> - - - - * * - - - - - - - - - - | - - * - | <-- |6weijiafai:2|quanjiaqi:6|~8~1
LC35 -> - - * - - - - - - - - - - - - - | - - * - | <-- |7weijiafai:1|quanjiaqi:3|7486:1|1~1
LC45 -> - - - * - - - - - - - - - - - - | - - * - | <-- |7weijiafai:1|quanjiaqi:4|7486:1|1~4
LC36 -> - - - - * * - - - - - - - - - - | - - * - | <-- |7weijiafai:1|quanjiaqi:6|~3~1
LC42 -> - - - - - - - - - - - * - - - - | - - * - | <-- |7weijiafai:1|quanjiaqi:6|CN~2
LC43 -> - - - - - - - - - - - * - - - - | - - * - | <-- |7weijiafai:1|quanjiaqi:6|CN~3
Pin
5 -> * * * * - - - * * * * * * * * - | - - * * | <-- M1
11 -> - * * * * * * * * * * * * * * * | - * * * | <-- M2
9 -> - - * * * * * * * * * * * * * * | - * * * | <-- M3
8 -> - - - * * * * * * - * * * * * * | - * * * | <-- M4
4 -> * * * * * * * * * * * * * * * * | - - * * | <-- N1
12 -> - * * * * * * * * * * * * * * * | - * * * | <-- N2
6 -> - - * * * * * * * * - * * * * * | - * * * | <-- N3
20 -> - - - * * * - - - - * * - - * * | - * * * | <-- N4
LC63 -> - - - * - - - - - - - - - - - - | - - * - | <-- |7weijiafai:1|quanjiaqi:4|7486:1|1~1
LC62 -> - - - * - - - - - - - - - - - - | - - * - | <-- |7weijiafai:1|quanjiaqi:4|7486:1|1~2
LC56 -> - - - * - - - - - - - - - - - - | - - * - | <-- |7weijiafai:1|quanjiaqi:4|7486:1|1~3
LC55 -> - - - * - - - - - - - - - - - - | - - * - | <-- |7weijiafai:1|quanjiaqi:4|7486:1|1~5
LC26 -> - - - - - - - - - - - * - - - - | - - * - | <-- |7weijiafai:1|quanjiaqi:6|CN~4
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\shiweichenfaqi\shiweichefa.rpt
shiweichefa
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC64 P5
| +----------------------------- LC63 |7weijiafai:1|quanjiaqi:4|7486:1|1~1
| | +--------------------------- LC62 |7weijiafai:1|quanjiaqi:4|7486:1|1~2
| | | +------------------------- LC56 |7weijiafai:1|quanjiaqi:4|7486:1|1~3
| | | | +----------------------- LC55 |7weijiafai:1|quanjiaqi:4|7486:1|1~5
| | | | | +--------------------- LC53 |7weijiafai:1|quanjiaqi:5|7486:1|1~1
| | | | | | +------------------- LC52 |7weijiafai:1|quanjiaqi:5|7486:1|1~2
| | | | | | | +----------------- LC51 |7weijiafai:1|quanjiaqi:5|7486:1|1~3
| | | | | | | | +--------------- LC50 |7weijiafai:1|quanjiaqi:5|7486:1|1~4
| | | | | | | | | +------------- LC49 |7weijiafai:1|quanjiaqi:5|7486:1|1~5
| | | | | | | | | | +----------- LC57 |7weijiafai:1|quanjiaqi:5|7486:1|1~6
| | | | | | | | | | | +--------- LC59 |7weijiafai:1|quanjiaqi:5|7486:1|1~7
| | | | | | | | | | | | +------- LC61 |7weijiafai:1|quanjiaqi:6|7486:1|1~1
| | | | | | | | | | | | | +----- LC54 |7weijiafai:1|quanjiaqi:6|7486:1|1~2
| | | | | | | | | | | | | | +--- LC58 |7weijiafai:1|quanjiaqi:6|7486:1|1~3
| | | | | | | | | | | | | | | +- LC60 |7weijiafai:1|quanjiaqi:6|7486:1|1~4
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC53 -> * - - - - - - - - - - - - - - - | - - - * | <-- |7weijiafai:1|quanjiaqi:5|7486:1|1~1
LC52 -> * - - - - - - - - - - - - - - - | - - - * | <-- |7weijiafai:1|quanjiaqi:5|7486:1|1~2
LC51 -> * - - - - - - - - - - - - - - - | - - - * | <-- |7weijiafai:1|quanjiaqi:5|7486:1|1~3
LC50 -> * - - - - - - - - - - - - - - - | - - - * | <-- |7weijiafai:1|quanjiaqi:5|7486:1|1~4
LC49 -> * - - - - - - - - - - - - - - - | - - - * | <-- |7weijiafai:1|quanjiaqi:5|7486:1|1~5
LC57 -> * - - - - - - - - - - - - - - - | - - - * | <-- |7weijiafai:1|quanjiaqi:5|7486:1|1~6
LC59 -> * - - - - - - - - - - - - - - - | - - - * | <-- |7weijiafai:1|quanjiaqi:5|7486:1|1~7
Pin
5 -> * * * * * * * * * * * * * * * * | - - * * | <-- M1
11 -> * * * * * * * * * * * * * * * * | - * * * | <-- M2
9 -> * * * * * * * * * * * * * * * * | - * * * | <-- M3
8 -> * * * * * * * * * * * * * * * * | - * * * | <-- M4
4 -> * * * * * * * * * * * * * * * * | - - * * | <-- N1
12 -> * * * * * * * * * * * * * * * * | - * * * | <-- N2
6 -> * * * * * * * * * * * * * * * * | - * * * | <-- N3
20 -> * * * * * * * * * * * * * * * * | - * * * | <-- N4
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\shiweichenfaqi\shiweichefa.rpt
shiweichefa
** EQUATIONS **
M1 : INPUT;
M2 : INPUT;
M3 : INPUT;
M4 : INPUT;
N1 : INPUT;
N2 : INPUT;
N3 : INPUT;
N4 : INPUT;
-- Node name is 'P1'
-- Equation name is 'P1', location is LC037, type is output.
P1 = LCELL( _EQ001 $ GND);
_EQ001 = M1 & N1;
-- Node name is 'P2'
-- Equation name is 'P2', location is LC040, type is output.
P2 = LCELL( _EQ002 $ GND);
_EQ002 = M2 & N1 & !N2
# !M1 & M2 & N1
# M1 & !N1 & N2
# M1 & !M2 & N2;
-- Node name is 'P3'
-- Equation name is 'P3', location is LC041, type is output.
P3 = LCELL( _EQ003 $ _EQ004);
_EQ003 = !_LC035 & !M1 & M2 & M3 & N1 & N2 & _X001
# !_LC035 & M1 & M2 & !N1 & N2 & N3 & _X001
# !_LC035 & M1 & M3 & N1 & N3 & _X001
# !_LC035 & M1 & !M3 & N1 & !N3 & _X001;
_X001 = EXP(!N1 & !N2 & !N3);
_EQ004 = !_LC035 & _X001;
_X001 = EXP(!N1 & !N2 & !N3);
-- Node name is 'P4'
-- Equation name is 'P4', location is LC046, type is output.
P4 = LCELL( _EQ005 $ _EQ006);
_EQ005 = !_LC045 & !_LC055 & !_LC056 & !_LC062 & !_LC063 & !M2 & M3 & !M4 &
N1 & !N2 & N3 & N4 & _X002 & _X003 & _X004
# !_LC045 & !_LC055 & !_LC056 & !_LC062 & !_LC063 & M2 & !M3 & !M4 &
N1 & N2 & !N3 & N4 & _X002 & _X003 & _X004
# !_LC045 & !_LC055 & !_LC056 & !_LC062 & !_LC063 & M1 & !M2 & M3 &
M4 & !N2 & N3 & !N4 & _X002 & _X003 & _X004
# !_LC045 & !_LC055 & !_LC056 & !_LC062 & !_LC063 & M1 & M2 & !M3 &
M4 & N2 & !N3 & !N4 & _X002 & _X003 & _X004;
_X002 = EXP( M2 & !M3 & M4 & N1 & !N2 & N3 & !N4);
_X003 = EXP(!M4 & !N2 & !N3 & !N4);
_X004 = EXP( M1 & !M2 & M3 & !M4 & N2 & !N3 & N4);
_EQ006 = !_LC045 & !_LC055 & !_LC056 & !_LC062 & !_LC063 & _X002 & _X003 &
_X004;
_X002 = EXP( M2 & !M3 & M4 & N1 & !N2 & N3 & !N4);
_X003 = EXP(!M4 & !N2 & !N3 & !N4);
_X004 = EXP( M1 & !M2 & M3 & !M4 & N2 & !N3 & N4);
-- Node name is 'P5'
-- Equation name is 'P5', location is LC064, type is output.
P5 = LCELL( _EQ007 $ VCC);
_EQ007 = !_LC049 & !_LC050 & !_LC051 & !_LC052 & !_LC053 & !_LC057 &
!_LC059 & _X002 & _X004;
_X002 = EXP( M2 & !M3 & M4 & N1 & !N2 & N3 & !N4);
_X004 = EXP( M1 & !M2 & M3 & !M4 & N2 & !N3 & N4);
-- Node name is 'P6'
-- Equation name is 'P6', location is LC017, type is output.
P6 = LCELL( _EQ008 $ VCC);
_EQ008 = !_LC034 & !_LC038 & !_LC054 & !_LC058 & !_LC060 & !_LC061 & _X005 &
_X006;
_X005 = EXP( M3 & !M4 & !N2 & !N3 & N4);
_X006 = EXP(!M2 & M3 & !N2 & !N3 & N4);
-- Node name is 'P7'
-- Equation name is 'P7', location is LC048, type is output.
P7 = LCELL( _EQ009 $ _LC036);
_EQ009 = !_LC039 & !_LC047 & M4 & N4 & _X007
# !N4 & _X008
# !M4 & _X008;
_X007 = EXP( M2 & M3 & M4 & N1 & N2 & N3);
_X008 = EXP(!_LC039 & !_LC044 & !_LC047);
-- Node name is 'P8'
-- Equation name is 'P8', location is LC033, type is output.
P8 = LCELL( _EQ010 $ _LC036);
_EQ010 = _LC036 & !_LC039 & !_LC047 & !N4 & _X007
# _LC036 & !_LC039 & !_LC047 & !M4 & _X007
# !_LC036 & M4 & N4 & _X008;
_X007 = EXP( M2 & M3 & M4 & N1 & N2 & N3);
_X008 = EXP(!_LC039 & !_LC044 & !_LC047);
-- Node name is '|6weijiafai:2|quanjiaqi:6|~2~1'
-- Equation name is '_LC044', type is buried
-- synthesized logic cell
_LC044 = LCELL( _EQ011 $ GND);
_EQ011 = M2 & M3 & M4 & N1 & N2 & N3;
-- Node name is '|6weijiafai:2|quanjiaqi:6|~7~1'
-- Equation name is '_LC047', type is buried
-- synthesized logic cell
_LC047 = LCELL( _EQ012 $ GND);
_EQ012 = !M1 & M2 & M4 & N1 & N2 & N3
# M1 & M3 & M4 & N1 & !N2 & N3
# M1 & M2 & M4 & !N1 & N2 & N3
# M2 & M3 & M4 & N1 & N3
# M3 & M4 & !N1 & N2 & N3;
-- Node name is '|6weijiafai:2|quanjiaqi:6|~8~1'
-- Equation name is '_LC039', type is buried
-- synthesized logic cell
_LC039 = LCELL( _EQ013 $ GND);
_EQ013 = M1 & M2 & M4 & N1 & N2 & N3
# M3 & M4 & N1 & N2 & N3;
-- Node name is '|7weijiafai:1|quanjiaqi:3|7486:1|~4~1' = '|7weijiafai:1|quanjiaqi:3|7486:1|1~1'
-- Equation name is '_LC035', type is buried
-- synthesized logic cell
_LC035 = LCELL( _EQ014 $ GND);
_EQ014 = !M1 & !M2 & !M3
# !M1 & !M2 & !N1
# !M1 & !N1 & !N2
# !M1 & !M3 & !N2
# !M2 & !N1 & !N3;
-- Node name is '|7weijiafai:1|quanjiaqi:4|7486:1|~4~1' = '|7weijiafai:1|quanjiaqi:4|7486:1|1~1'
-- Equation name is '_LC063', type is buried
-- synthesized logic cell
_LC063 = LCELL( _EQ015 $ GND);
_EQ015 = !M2 & M3 & M4 & N1 & N2 & !N3 & !N4
# M1 & M2 & !M3 & !M4 & !N2 & N3 & N4
# M2 & M4 & N1 & N2 & N3 & N4
# M3 & M4 & N1 & N2 & N3 & N4
# M1 & M2 & M3 & M4 & N1 & N4;
-- Node name is '|7weijiafai:1|quanjiaqi:4|7486:1|~4~2' = '|7weijiafai:1|quanjiaqi:4|7486:1|1~2'
-- Equation name is '_LC062', type is buried
-- synthesized logic cell
_LC062 = LCELL( _EQ016 $ GND);
_EQ016 = M1 & !M4 & N1 & N2 & N3 & !N4
# M1 & M2 & M3 & !M4 & N1 & !N4
# !M1 & !M2 & M3 & M4 & N1 & N2
# !M1 & M2 & M3 & !N1 & N2 & N3
# M1 & M4 & N1 & !N2 & !N3 & N4;
-- Node name is '|7weijiafai:1|quanjiaqi:4|7486:1|~4~3' = '|7weijiafai:1|quanjiaqi:4|7486:1|1~3'
-- Equation name is '_LC056', type is buried
-- synthesized logic cell
_LC056 = LCELL( _EQ017 $ GND);
_EQ017 = M1 & !M2 & !M3 & M4 & N1 & N4
# M1 & M2 & !N1 & !N2 & N3 & N4
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