5weijiafai.rpt

maxplus做的四位乘法器

        | | | | | +----------- LC22 Q1
        | | | | | | +--------- LC21 Q2
        | | | | | | | +------- LC20 Q3
        | | | | | | | | +----- LC19 Q4
        | | | | | | | | | +--- LC18 Q5
        | | | | | | | | | | +- LC17 Q6
        | | | | | | | | | | | 
        | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC25 -> - - - - - - - - * - - | - * | <-- |quanjiaqi:4|7486:1|1~1
LC26 -> - - - - - - - - * - - | - * | <-- |quanjiaqi:4|7486:1|1~2
LC23 -> - - - - - - - - - * - | - * | <-- |quanjiaqi:5|7486:1|1~1
LC29 -> - - - - - - - - - * - | - * | <-- |quanjiaqi:5|7486:1|1~2
LC24 -> - - - - - - - - - * - | - * | <-- |quanjiaqi:5|7486:1|1~3

Pin
4    -> * - * * - * * * - - * | - * | <-- A1
14   -> * * * * * - * * - - * | - * | <-- A2
13   -> * * * * * - - * - - * | - * | <-- A3
12   -> - - * * * - - - * - * | - * | <-- A4
11   -> - - - - - - - - - * * | - * | <-- A5
9    -> * - * * - * * * - - * | - * | <-- B1
8    -> * * * * * - * * - - * | - * | <-- B2
7    -> * * * * * - - * - - * | - * | <-- B3
6    -> - - * * * - - - * - * | - * | <-- B4
5    -> - - - - - - - - - * * | - * | <-- B5


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                  f:\shiweichenfaqi\5weijiafai.rpt
5weijiafai

** EQUATIONS **

A1       : INPUT;
A2       : INPUT;
A3       : INPUT;
A4       : INPUT;
A5       : INPUT;
B1       : INPUT;
B2       : INPUT;
B3       : INPUT;
B4       : INPUT;
B5       : INPUT;

-- Node name is 'Q1' 
-- Equation name is 'Q1', location is LC022, type is output.
 Q1      = LCELL( B1 $  A1);

-- Node name is 'Q2' 
-- Equation name is 'Q2', location is LC021, type is output.
 Q2      = LCELL( _EQ001 $  A2);
  _EQ001 =  A1 &  B1 & !B2
         # !B1 &  B2
         # !A1 &  B2;

-- Node name is 'Q3' 
-- Equation name is 'Q3', location is LC020, type is output.
 Q3      = LCELL( _EQ002 $  A3);
  _EQ002 =  A1 &  B1 & !B3 &  _X001
         #  A2 &  B2 & !B3
         # !A2 &  B3 &  _X002
         # !B2 &  B3 &  _X003;
  _X001  = EXP(!A2 & !B2);
  _X002  = EXP( A1 &  B1 &  B2);
  _X003  = EXP( A1 &  B1);

-- Node name is 'Q4' 
-- Equation name is 'Q4', location is LC019, type is output.
 Q4      = LCELL( _EQ003 $  _EQ004);
  _EQ003 =  _X004 &  _X005;
  _X004  = EXP(!A4 &  B4);
  _X005  = EXP( A4 & !B4);
  _EQ004 = !_LC025 & !_LC026;

-- Node name is 'Q5' 
-- Equation name is 'Q5', location is LC018, type is output.
 Q5      = LCELL( _EQ005 $  _EQ006);
  _EQ005 =  _X006 &  _X007;
  _X006  = EXP(!A5 &  B5);
  _X007  = EXP( A5 & !B5);
  _EQ006 = !_LC023 & !_LC024 & !_LC029;

-- Node name is 'Q6' 
-- Equation name is 'Q6', location is LC017, type is output.
 Q6      = LCELL( _EQ007 $  GND);
  _EQ007 =  A1 &  B1 &  _X001 &  _X008 &  _X009 &  _X010
         #  A2 &  B2 &  _X008 &  _X009 &  _X010
         #  A3 &  B3 &  _X009 &  _X010
         #  A4 &  B4 &  _X010
         #  A5 &  B5;
  _X001  = EXP(!A2 & !B2);
  _X008  = EXP(!A3 & !B3);
  _X009  = EXP(!A4 & !B4);
  _X010  = EXP(!A5 & !B5);

-- Node name is '|quanjiaqi:4|7486:1|~4~1' = '|quanjiaqi:4|7486:1|1~1' 
-- Equation name is '_LC025', type is buried 
-- synthesized logic cell 
_LC025   = LCELL( _EQ008 $  GND);
  _EQ008 =  A1 &  B1 &  B2 &  B3
         #  A1 &  A2 &  B1 &  B3
         #  A1 &  A3 &  B1 &  B2
         #  A1 &  A2 &  A3 &  B1
         #  A2 &  B2 &  B3;

-- Node name is '|quanjiaqi:4|7486:1|~4~2' = '|quanjiaqi:4|7486:1|1~2' 
-- Equation name is '_LC026', type is buried 
-- synthesized logic cell 
_LC026   = LCELL( _EQ009 $  GND);
  _EQ009 =  A2 &  A3 &  B2
         #  A3 &  B3;

-- Node name is '|quanjiaqi:5|7486:1|~4~1' = '|quanjiaqi:5|7486:1|1~1' 
-- Equation name is '_LC023', type is buried 
-- synthesized logic cell 
_LC023   = LCELL( _EQ010 $  GND);
  _EQ010 =  A1 &  B1 &  B2 &  B3 &  B4
         #  A1 &  A2 &  B1 &  B3 &  B4
         #  A1 &  A3 &  B1 &  B2 &  B4
         #  A1 &  A2 &  A3 &  B1 &  B4
         #  A1 &  A4 &  B1 &  B2 &  B3;

-- Node name is '|quanjiaqi:5|7486:1|~4~2' = '|quanjiaqi:5|7486:1|1~2' 
-- Equation name is '_LC029', type is buried 
-- synthesized logic cell 
_LC029   = LCELL( _EQ011 $  GND);
  _EQ011 =  A1 &  A2 &  A4 &  B1 &  B3
         #  A1 &  A3 &  A4 &  B1 &  B2
         #  A1 &  A2 &  A3 &  A4 &  B1
         #  A2 &  B2 &  B3 &  B4
         #  A2 &  A3 &  B2 &  B4;

-- Node name is '|quanjiaqi:5|7486:1|~4~3' = '|quanjiaqi:5|7486:1|1~3' 
-- Equation name is '_LC024', type is buried 
-- synthesized logic cell 
_LC024   = LCELL( _EQ012 $  GND);
  _EQ012 =  A2 &  A4 &  B2 &  B3
         #  A2 &  A3 &  A4 &  B2
         #  A3 &  B3 &  B4
         #  A3 &  A4 &  B3
         #  A4 &  B4;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                           f:\shiweichenfaqi\5weijiafai.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,080K