📄 7weijiafai.rpt
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# A1 & A5 & B1 & B2 & B3 & B4 & B6
# A1 & A2 & A5 & B1 & B3 & B4 & B6;
-- Node name is '|quanjiaqi:6|~3~4' = '|quanjiaqi:6|CN~4'
-- Equation name is '_LC054', type is buried
-- synthesized logic cell
_LC054 = LCELL( _EQ018 $ GND);
_EQ018 = A1 & A3 & A5 & B1 & B2 & B4 & B6
# A1 & A2 & A3 & A5 & B1 & B4 & B6
# A1 & A4 & A5 & B1 & B2 & B3 & B6
# A1 & A2 & A4 & A5 & B1 & B3 & B6
# A1 & A3 & A4 & A5 & B1 & B2 & B6;
-- Node name is '|quanjiaqi:6|~3~5' = '|quanjiaqi:6|CN~5'
-- Equation name is '_LC047', type is buried
-- synthesized logic cell
_LC047 = LCELL( _EQ019 $ GND);
_EQ019 = A1 & A2 & A3 & A4 & A5 & B1 & B6
# A1 & A6 & B1 & B2 & B3 & B4 & B5
# A1 & A2 & A6 & B1 & B3 & B4 & B5
# A1 & A3 & A6 & B1 & B2 & B4 & B5
# A1 & A2 & A3 & A6 & B1 & B4 & B5;
-- Node name is '|quanjiaqi:6|~3~6' = '|quanjiaqi:6|CN~6'
-- Equation name is '_LC041', type is buried
-- synthesized logic cell
_LC041 = LCELL( _EQ020 $ GND);
_EQ020 = A1 & A4 & A6 & B1 & B2 & B3 & B5
# A1 & A2 & A4 & A6 & B1 & B3 & B5
# A1 & A3 & A4 & A6 & B1 & B2 & B5
# A1 & A2 & A3 & A4 & A6 & B1 & B5
# A1 & A5 & A6 & B1 & B2 & B3 & B4;
-- Node name is '|quanjiaqi:6|~3~7' = '|quanjiaqi:6|CN~7'
-- Equation name is '_LC044', type is buried
-- synthesized logic cell
_LC044 = LCELL( _EQ021 $ GND);
_EQ021 = A1 & A2 & A5 & A6 & B1 & B3 & B4
# A1 & A3 & A5 & A6 & B1 & B2 & B4
# A1 & A2 & A3 & A5 & A6 & B1 & B4
# A1 & A4 & A5 & A6 & B1 & B2 & B3
# A1 & A2 & A4 & A5 & A6 & B1 & B3;
-- Node name is '|quanjiaqi:6|~3~8' = '|quanjiaqi:6|CN~8'
-- Equation name is '_LC048', type is buried
-- synthesized logic cell
_LC048 = LCELL( _EQ022 $ GND);
_EQ022 = A1 & A3 & A4 & A5 & A6 & B1 & B2
# A1 & A2 & A3 & A4 & A5 & A6 & B1
# A2 & B2 & B3 & B4 & B5 & B6
# A2 & A3 & B2 & B4 & B5 & B6
# A2 & A4 & B2 & B3 & B5 & B6;
-- Node name is '|quanjiaqi:6|~3~9' = '|quanjiaqi:6|CN~9'
-- Equation name is '_LC045', type is buried
-- synthesized logic cell
_LC045 = LCELL( _EQ023 $ GND);
_EQ023 = A2 & A3 & A4 & B2 & B5 & B6
# A2 & A5 & B2 & B3 & B4 & B6
# A2 & A3 & A5 & B2 & B4 & B6
# A2 & A4 & A5 & B2 & B3 & B6
# A2 & A3 & A4 & A5 & B2 & B6;
-- Node name is '|quanjiaqi:6|~3~10' = '|quanjiaqi:6|CN~10'
-- Equation name is '_LC046', type is buried
-- synthesized logic cell
_LC046 = LCELL( _EQ024 $ GND);
_EQ024 = A2 & A6 & B2 & B3 & B4 & B5
# A2 & A3 & A6 & B2 & B4 & B5
# A2 & A4 & A6 & B2 & B3 & B5
# A2 & A3 & A4 & A6 & B2 & B5
# A2 & A5 & A6 & B2 & B3 & B4;
-- Node name is '|quanjiaqi:6|~3~11' = '|quanjiaqi:6|CN~11'
-- Equation name is '_LC039', type is buried
-- synthesized logic cell
_LC039 = LCELL( _EQ025 $ GND);
_EQ025 = A2 & A3 & A5 & A6 & B2 & B4
# A2 & A4 & A5 & A6 & B2 & B3
# A2 & A3 & A4 & A5 & A6 & B2
# A3 & B3 & B4 & B5 & B6
# A3 & A4 & B3 & B5 & B6;
-- Node name is '|quanjiaqi:6|~3~12' = '|quanjiaqi:6|CN~12'
-- Equation name is '_LC038', type is buried
-- synthesized logic cell
_LC038 = LCELL( _EQ026 $ GND);
_EQ026 = A3 & A5 & B3 & B4 & B6
# A3 & A4 & A5 & B3 & B6
# A3 & A6 & B3 & B4 & B5
# A3 & A4 & A6 & B3 & B5
# A3 & A5 & A6 & B3 & B4;
-- Node name is '|quanjiaqi:6|~3~13' = '|quanjiaqi:6|CN~13'
-- Equation name is '_LC034', type is buried
-- synthesized logic cell
_LC034 = LCELL( _EQ027 $ GND);
_EQ027 = A3 & A4 & A5 & A6 & B3
# A4 & B4 & B5 & B6
# A4 & A5 & B4 & B6
# A4 & A6 & B4 & B5
# A4 & A5 & A6 & B4;
-- Node name is '|quanjiaqi:6|~3~14' = '|quanjiaqi:6|CN~14'
-- Equation name is '_LC035', type is buried
-- synthesized logic cell
_LC035 = LCELL( _EQ028 $ GND);
_EQ028 = A5 & B5 & B6
# A5 & A6 & B5
# A6 & B6;
-- Node name is '|quanjiaqi:6|~3~1'
-- Equation name is '_LC058', type is buried
-- synthesized logic cell
_LC058 = LCELL( _EQ029 $ VCC);
_EQ029 = !_LC034 & !_LC035 & !_LC038 & !_LC039 & !_LC041 & !_LC044 &
!_LC045 & !_LC046 & !_LC047 & !_LC048 & !_LC054 & !_LC060 &
!_LC063;
-- Node name is '|quanjiaqi:6|7486:1|~4~1' = '|quanjiaqi:6|7486:1|1~1'
-- Equation name is '_LC052', type is buried
-- synthesized logic cell
_LC052 = LCELL( _EQ030 $ GND);
_EQ030 = A1 & B1 & B2 & B3 & B4 & B5
# A1 & A2 & B1 & B3 & B4 & B5
# A1 & A3 & B1 & B2 & B4 & B5
# A1 & A2 & A3 & B1 & B4 & B5
# A1 & A4 & B1 & B2 & B3 & B5;
-- Node name is '|quanjiaqi:6|7486:1|~4~2' = '|quanjiaqi:6|7486:1|1~2'
-- Equation name is '_LC051', type is buried
-- synthesized logic cell
_LC051 = LCELL( _EQ031 $ GND);
_EQ031 = A1 & A2 & A4 & B1 & B3 & B5
# A1 & A3 & A4 & B1 & B2 & B5
# A1 & A2 & A3 & A4 & B1 & B5
# A1 & A5 & B1 & B2 & B3 & B4
# A1 & A2 & A5 & B1 & B3 & B4;
-- Node name is '|quanjiaqi:6|7486:1|~4~3' = '|quanjiaqi:6|7486:1|1~3'
-- Equation name is '_LC050', type is buried
-- synthesized logic cell
_LC050 = LCELL( _EQ032 $ GND);
_EQ032 = A1 & A3 & A5 & B1 & B2 & B4
# A1 & A2 & A3 & A5 & B1 & B4
# A1 & A4 & A5 & B1 & B2 & B3
# A1 & A2 & A4 & A5 & B1 & B3
# A1 & A3 & A4 & A5 & B1 & B2;
-- Node name is '|quanjiaqi:6|7486:1|~4~4' = '|quanjiaqi:6|7486:1|1~4'
-- Equation name is '_LC049', type is buried
-- synthesized logic cell
_LC049 = LCELL( _EQ033 $ GND);
_EQ033 = A1 & A2 & A3 & A4 & A5 & B1
# A2 & B2 & B3 & B4 & B5
# A2 & A3 & B2 & B4 & B5
# A2 & A4 & B2 & B3 & B5
# A2 & A3 & A4 & B2 & B5;
-- Node name is '|quanjiaqi:6|7486:1|~4~5' = '|quanjiaqi:6|7486:1|1~5'
-- Equation name is '_LC033', type is buried
-- synthesized logic cell
_LC033 = LCELL( _EQ034 $ GND);
_EQ034 = A2 & A5 & B2 & B3 & B4
# A2 & A3 & A5 & B2 & B4
# A2 & A4 & A5 & B2 & B3
# A2 & A3 & A4 & A5 & B2
# A3 & B3 & B4 & B5;
-- Node name is '|quanjiaqi:6|7486:1|~4~6' = '|quanjiaqi:6|7486:1|1~6'
-- Equation name is '_LC036', type is buried
-- synthesized logic cell
_LC036 = LCELL( _EQ035 $ GND);
_EQ035 = A3 & A4 & B3 & B5
# A3 & A5 & B3 & B4
# A3 & A4 & A5 & B3
# A4 & B4 & B5
# A4 & A5 & B4;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information f:\shiweichenfaqi\7weijiafai.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,331K
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