📄 6weijiafai.rpt
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Device-Specific Information: f:\shiweichenfaqi\6weijiafai.rpt
6weijiafai
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------------------------- LC2 |quanjiaqi:4|7486:1|1~2
| +----------------------------- LC4 |quanjiaqi:4|7486:1|1~3
| | +--------------------------- LC7 |quanjiaqi:5|7486:1|1~3
| | | +------------------------- LC11 |quanjiaqi:6|CN~5
| | | | +----------------------- LC10 |quanjiaqi:6|CN~6
| | | | | +--------------------- LC9 |quanjiaqi:6|CN~8
| | | | | | +------------------- LC3 |quanjiaqi:6|CN~9
| | | | | | | +----------------- LC1 |quanjiaqi:6|CN~10
| | | | | | | | +--------------- LC16 |quanjiaqi:6|CN~11
| | | | | | | | | +------------- LC6 |quanjiaqi:6|CN~12
| | | | | | | | | | +----------- LC5 |quanjiaqi:6|CN~13
| | | | | | | | | | | +--------- LC8 |quanjiaqi:6|7486:1|1~5
| | | | | | | | | | | | +------- LC12 |quanjiaqi:6|7486:1|1~6
| | | | | | | | | | | | | +----- LC13 Q4
| | | | | | | | | | | | | | +--- LC14 Q5
| | | | | | | | | | | | | | | +- LC15 Q6
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'A':
LC2 -> - - - - - - - - - - - - - * - - | * - | <-- |quanjiaqi:4|7486:1|1~2
LC4 -> - - - - - - - - - - - - - * - - | * - | <-- |quanjiaqi:4|7486:1|1~3
LC7 -> - - - - - - - - - - - - - - * - | * - | <-- |quanjiaqi:5|7486:1|1~3
LC8 -> - - - - - - - - - - - - - - - * | * - | <-- |quanjiaqi:6|7486:1|1~5
LC12 -> - - - - - - - - - - - - - - - * | * - | <-- |quanjiaqi:6|7486:1|1~6
Pin
38 -> - - - * * - - - - - - - - - - - | * * | <-- A1
17 -> * - * * * * * * - - - * - - - - | * * | <-- A2
16 -> * - * * * * * * * * - * * - - - | * * | <-- A3
14 -> - * * * * * * * * * - * * - - - | * * | <-- A4
13 -> - - - * * * * * * * * * * - * * | * * | <-- A5
12 -> - - - * * - * * * * * - - - - * | * * | <-- A6
11 -> - - - * * - - - - - - - - - - - | * * | <-- B1
9 -> * - * * * * * * - - - * - - - - | * * | <-- B2
8 -> * - * * * * * * * * - * * - - - | * * | <-- B3
7 -> - * * * * * * * * * - * * - - - | * * | <-- B4
6 -> - - - * - * * * * * * * * - * * | * * | <-- B5
21 -> - - - - - * - * * * * - - - - * | * * | <-- B6
LC25 -> - - - - - - - - - - - - - * - - | * - | <-- |quanjiaqi:4|7486:1|1~1
LC29 -> - - - - - - - - - - - - - - * - | * - | <-- |quanjiaqi:5|7486:1|1~1
LC26 -> - - - - - - - - - - - - - - * - | * - | <-- |quanjiaqi:5|7486:1|1~2
LC23 -> - - - - - - - - - - - - - - - * | * - | <-- |quanjiaqi:6|7486:1|1~1
LC22 -> - - - - - - - - - - - - - - - * | * - | <-- |quanjiaqi:6|7486:1|1~2
LC21 -> - - - - - - - - - - - - - - - * | * - | <-- |quanjiaqi:6|7486:1|1~3
LC20 -> - - - - - - - - - - - - - - - * | * - | <-- |quanjiaqi:6|7486:1|1~4
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\shiweichenfaqi\6weijiafai.rpt
6weijiafai
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC25 |quanjiaqi:4|7486:1|1~1
| +----------------------------- LC29 |quanjiaqi:5|7486:1|1~1
| | +--------------------------- LC26 |quanjiaqi:5|7486:1|1~2
| | | +------------------------- LC27 |quanjiaqi:6|CN~1
| | | | +----------------------- LC28 |quanjiaqi:6|CN~2
| | | | | +--------------------- LC30 |quanjiaqi:6|CN~3
| | | | | | +------------------- LC32 |quanjiaqi:6|CN~4
| | | | | | | +----------------- LC31 |quanjiaqi:6|CN~7
| | | | | | | | +--------------- LC23 |quanjiaqi:6|7486:1|1~1
| | | | | | | | | +------------- LC22 |quanjiaqi:6|7486:1|1~2
| | | | | | | | | | +----------- LC21 |quanjiaqi:6|7486:1|1~3
| | | | | | | | | | | +--------- LC20 |quanjiaqi:6|7486:1|1~4
| | | | | | | | | | | | +------- LC17 Q1
| | | | | | | | | | | | | +----- LC18 Q2
| | | | | | | | | | | | | | +--- LC19 Q3
| | | | | | | | | | | | | | | +- LC24 Q7
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC27 -> - - - - - - - - - - - - - - - * | - * | <-- |quanjiaqi:6|CN~1
LC28 -> - - - - - - - - - - - - - - - * | - * | <-- |quanjiaqi:6|CN~2
LC30 -> - - - - - - - - - - - - - - - * | - * | <-- |quanjiaqi:6|CN~3
LC32 -> - - - - - - - - - - - - - - - * | - * | <-- |quanjiaqi:6|CN~4
LC31 -> - - - - - - - - - - - - - - - * | - * | <-- |quanjiaqi:6|CN~7
Pin
38 -> * * * * * * * * * * * * * * * - | * * | <-- A1
17 -> * * * * * * * * * * * * - * * - | * * | <-- A2
16 -> * * * * * * * * * * * * - - * - | * * | <-- A3
14 -> - * * * * * * * * * * * - - - - | * * | <-- A4
13 -> - - - - * * * * - * * * - - - - | * * | <-- A5
12 -> - - - - - - * * - - - - - - - - | * * | <-- A6
11 -> * * * * * * * * * * * * * * * - | * * | <-- B1
9 -> * * * * * * * * * * * * - * * - | * * | <-- B2
8 -> * * * * * * * * * * * * - - * - | * * | <-- B3
7 -> - * * * * * * * * * * * - - - - | * * | <-- B4
6 -> - - - * * - * * * * - * - - - - | * * | <-- B5
21 -> - - - * * * * * - - - - - - - - | * * | <-- B6
LC11 -> - - - - - - - - - - - - - - - * | - * | <-- |quanjiaqi:6|CN~5
LC10 -> - - - - - - - - - - - - - - - * | - * | <-- |quanjiaqi:6|CN~6
LC9 -> - - - - - - - - - - - - - - - * | - * | <-- |quanjiaqi:6|CN~8
LC3 -> - - - - - - - - - - - - - - - * | - * | <-- |quanjiaqi:6|CN~9
LC1 -> - - - - - - - - - - - - - - - * | - * | <-- |quanjiaqi:6|CN~10
LC16 -> - - - - - - - - - - - - - - - * | - * | <-- |quanjiaqi:6|CN~11
LC6 -> - - - - - - - - - - - - - - - * | - * | <-- |quanjiaqi:6|CN~12
LC5 -> - - - - - - - - - - - - - - - * | - * | <-- |quanjiaqi:6|CN~13
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\shiweichenfaqi\6weijiafai.rpt
6weijiafai
** EQUATIONS **
A1 : INPUT;
A2 : INPUT;
A3 : INPUT;
A4 : INPUT;
A5 : INPUT;
A6 : INPUT;
B1 : INPUT;
B2 : INPUT;
B3 : INPUT;
B4 : INPUT;
B5 : INPUT;
B6 : INPUT;
-- Node name is 'Q1'
-- Equation name is 'Q1', location is LC017, type is output.
Q1 = LCELL( B1 $ A1);
-- Node name is 'Q2'
-- Equation name is 'Q2', location is LC018, type is output.
Q2 = LCELL( _EQ001 $ A2);
_EQ001 = A1 & B1 & !B2
# !B1 & B2
# !A1 & B2;
-- Node name is 'Q3'
-- Equation name is 'Q3', location is LC019, type is output.
Q3 = LCELL( _EQ002 $ A3);
_EQ002 = A1 & B1 & !B3 & _X001
# A2 & B2 & !B3
# !A2 & B3 & _X002
# !B2 & B3 & _X003;
_X001 = EXP(!A2 & !B2);
_X002 = EXP( A1 & B1 & B2);
_X003 = EXP( A1 & B1);
-- Node name is 'Q4'
-- Equation name is 'Q4', location is LC013, type is output.
Q4 = LCELL(!_LC004 $ _EQ003);
_EQ003 = !_LC002 & !_LC025;
-- Node name is 'Q5'
-- Equation name is 'Q5', location is LC014, type is output.
Q5 = LCELL( _EQ004 $ _EQ005);
_EQ004 = _X004 & _X005;
_X004 = EXP(!A5 & B5);
_X005 = EXP( A5 & !B5);
_EQ005 = !_LC007 & !_LC026 & !_LC029;
-- Node name is 'Q6'
-- Equation name is 'Q6', location is LC015, type is output.
Q6 = LCELL( _EQ006 $ _EQ007);
_EQ006 = _X006 & _X007;
_X006 = EXP(!A6 & B6);
_X007 = EXP( A6 & !B6);
_EQ007 = !_LC008 & !_LC012 & !_LC020 & !_LC021 & !_LC022 & !_LC023 & _X008;
_X008 = EXP( A5 & B5);
-- Node name is 'Q7'
-- Equation name is 'Q7', location is LC024, type is output.
Q7 = LCELL( _EQ008 $ VCC);
_EQ008 = !_LC001 & !_LC003 & !_LC005 & !_LC006 & !_LC009 & !_LC010 &
!_LC011 & !_LC016 & !_LC027 & !_LC028 & !_LC030 & !_LC031 &
!_LC032;
-- Node name is '|quanjiaqi:4|7486:1|~4~1' = '|quanjiaqi:4|7486:1|1~1'
-- Equation name is '_LC025', type is buried
-- synthesized logic cell
_LC025 = LCELL( _EQ009 $ GND);
_EQ009 = A1 & B1 & B2 & B3
# A1 & A2 & B1 & B3
# A1 & A3 & B1 & B2
# A1 & A2 & A3 & B1
# A2 & B2 & B3;
-- Node name is '|quanjiaqi:4|7486:1|~4~2' = '|quanjiaqi:4|7486:1|1~2'
-- Equation name is '_LC002', type is buried
-- synthesized logic cell
_LC002 = LCELL( _EQ010 $ GND);
_EQ010 = A2 & A3 & B2
# A3 & B3;
-- Node name is '|quanjiaqi:4|7486:1|~4~3' = '|quanjiaqi:4|7486:1|1~3'
-- Equation name is '_LC004', type is buried
-- synthesized logic cell
_LC004 = LCELL( _EQ011 $ GND);
_EQ011 = A4 & !B4
# !A4 & B4;
-- Node name is '|quanjiaqi:5|7486:1|~4~1' = '|quanjiaqi:5|7486:1|1~1'
-- Equation name is '_LC029', type is buried
-- synthesized logic cell
_LC029 = LCELL( _EQ012 $ GND);
_EQ012 = A1 & B1 & B2 & B3 & B4
# A1 & A2 & B1 & B3 & B4
# A1 & A3 & B1 & B2 & B4
# A1 & A2 & A3 & B1 & B4
# A1 & A4 & B1 & B2 & B3;
-- Node name is '|quanjiaqi:5|7486:1|~4~2' = '|quanjiaqi:5|7486:1|1~2'
-- Equation name is '_LC026', type is buried
-- synthesized logic cell
_LC026 = LCELL( _EQ013 $ GND);
_EQ013 = A1 & A2 & A4 & B1 & B3
# A1 & A3 & A4 & B1 & B2
# A1 & A2 & A3 & A4 & B1
# A2 & B2 & B3 & B4
# A2 & A3 & B2 & B4;
-- Node name is '|quanjiaqi:5|7486:1|~4~3' = '|quanjiaqi:5|7486:1|1~3'
-- Equation name is '_LC007', type is buried
-- synthesized logic cell
_LC007 = LCELL( _EQ014 $ GND);
_EQ014 = A2 & A4 & B2 & B3
# A2 & A3 & A4 & B2
# A3 & B3 & B4
# A3 & A4 & B3
# A4 & B4;
-- Node name is '|quanjiaqi:6|~3~1' = '|quanjiaqi:6|CN~1'
-- Equation name is '_LC027', type is buried
-- synthesized logic cell
_LC027 = LCELL( _EQ015 $ GND);
_EQ015 = A1 & B1 & B2 & B3 & B4 & B5 & B6
# A1 & A2 & B1 & B3 & B4 & B5 & B6
# A1 & A3 & B1 & B2 & B4 & B5 & B6
# A1 & A2 & A3 & B1 & B4 & B5 & B6
# A1 & A4 & B1 & B2 & B3 & B5 & B6;
-- Node name is '|quanjiaqi:6|~3~2' = '|quanjiaqi:6|CN~2'
-- Equation name is '_LC028', type is buried
-- synthesized logic cell
_LC028 = LCELL( _EQ016 $ GND);
_EQ016 = A1 & A2 & A4 & B1 & B3 & B5 & B6
# A1 & A3 & A4 & B1 & B2 & B5 & B6
# A1 & A2 & A3 & A4 & B1 & B5 & B6
# A1 & A5 & B1 & B2 & B3 & B4 & B6
# A1 & A2 & A5 & B1 & B3 & B4 & B6;
-- Node name is '|quanjiaqi:6|~3~3' = '|quanjiaqi:6|CN~3'
-- Equation name is '_LC030', type is buried
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