tb_cc.v

来自「FPGA的一个学习用的代码。主要表示了验证环境的搭建」· Verilog 代码 · 共 34 行

module tb_cc();

reg    sys_clk;
reg    sys_rst;

initial
begin
  sys_clk = 0;
  sys_rst = 1;
  #30
  sys_rst = 0;
  
  #100
  $display("call task of write register at address:10'h1 with data:32'hff");
  u_bfm_cc.cpu_wt_reg(1,32'hff);
  
  #10
  $display("call task of read register at address:10'h2");
  u_bfm_cc.cpu_rd_reg(2);
    

    
end

always #5 sys_clk = !sys_clk;

bfm_cc u_bfm_cc
(
 .sys_clk (sys_clk)

);


endmodule