sram32kx16.vhd

cpu86是用VHDL描述的8088IP核

--*****************************************************************************
-- sram256Kx16.vhd 
-- Simple memory model
--****************************************************************************
use std.textio.all;
Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity sram32kx16 is
  generic (tacc : time := 15 ns;				   		-- Access Time
	       thold: time := 5 ns);						-- Hold time to Z
  port (         				-- not chip select 1, cs2
        addr    : in    std_logic_vector(17 downto 0); 
        data    : inout std_logic_vector(15 downto 0);
		we      : in    std_logic;						-- not write enable
		oe      : in    std_logic;						-- not output enable
		cs      : in    std_logic;
        ble     : in    std_logic;  					-- not write enable 
        bhe     : in    std_logic);  					-- not write enable 
end sram32kx16;

architecture behaviour of sram32kx16 is

 constant low_address: natural := 0;
 constant high_address: natural := 262144;  -- 512K byte SRAM

 subtype word is std_logic_vector(15 downto 0);

 type memory_array is
      array (natural range low_address to high_address) of word;

 signal addr_s : std_logic_vector(18 downto 0);
 signal data_s : std_logic_vector(15 downto 0);

begin

  addr_s <= '0'&addr;
  
  process (cs,oe,we,addr_s,data, ble, bhe)
              
     variable mem: memory_array;
     variable address : natural;           
      
   begin  
    
       if (cs = '0') then
       		address := conv_integer(addr_s);

	      	if (oe='0' and (ble='0' or bhe='0')) then							-- Read Cycle
	      	  	data_s <= mem(address); 	-- Read Word

	           	if ble='0' then  
	           		data(7 downto 0) <= data_s(7 downto 0) after tacc;
	           	end if;
	           	if bhe='0' then
					data(15 downto 8) <= data_s(15 downto 8) after tacc;
	           	end if;
	         	   		         	 
	        elsif (we='0' and (ble='0' or bhe='0')) then		-- write cycle
	         	if ble='0' then  
	         		mem(address)(7 downto 0) := data(7 downto 0);
	         	end if;
	         	if bhe='0' then
	         		mem(address)(15 downto 8) := data(15 downto 8);
	         	end if;
	        else
	         	data <= (others => 'Z') after thold;         
	        end if;	      
       else 
       	  data <= (others => 'Z') after thold;	-- CS not asserted    
       end if;  
    
    end process;

end behaviour;