uart9_readme.txt

This the 8th release of PicoBlaze for Spartan-3, Spartan-3E Virtex-II, Virtex-IIPro and Virtex-4 d

  end process parity_tx_port;

  -- PORT 10 : Write data to UART transmitter. 
  write_to_uart <= write_strobe and port_id(4);

  tx_data <= tx_parity & out_port;

  transmit: uart9_tx 
  port map (            data_in => tx_data, 
                   write_buffer => write_to_uart,
                   reset_buffer => reset_buffer,
                   en_16_x_baud => en_16_x_baud,
                     serial_out => serial_out,
                    buffer_full => buffer_full,
               buffer_half_full => buffer_half_full,
                            clk => clk );

...............

  --UART Receiver interface

  input_ports: process(clk)
  begin
    if clk'event and clk='1' then

      case port_id(1 downto 0) is

        --PORT 00 : Read FIFO status including receiver parity bit 
        when "00" =>    in_port <= uart_status;  

        --PORT 01 : Read receiver UART 
        when "01" =>    in_port <= rx_data(7 downto 0);

        --PORT 02 - if required
        --when "10" =>    in_port <= ?????;

        --PORT 03 - if required
        --when "11" =>    in_port <= ?????;

        -- Don't care used to ensure minimum logic
        when others =>    in_port <= "XXXXXXXX";  

      end case;

      -- Form read strobe for UART receiver FIFO buffer for address 01.

      read_from_uart <= read_strobe and (not port_id(1)) and port_id(0); 

    end if;

  receive: uart9_rx
  port map (            serial_in => rx,
                         data_out => rx_data,
                      read_buffer => read_from_uart,
                     reset_buffer => rx_reset,
                     en_16_x_baud => en_38400_baud,
              buffer_data_present => rx_data_present,
                      buffer_full => rx_full,
                 buffer_half_full => rx_half_full,
                              clk => clk );  


  uart_status <= rx_data(8) & "00" & rx_full & rx_half_full & rx_data_present & tx_full & tx_half_full ;



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PicoBlaze to uart9_tx PSM code example    

The following sections of PSM code relate to the VHDL interface above and enable a byte 
of data to be transmitted or received via the UART including parity. CONSTANT directives
have been used to define both the port numbers and the allocations of bits within a given
port.

The parity generation is performed by the TEST instruction. It is vital that the 
transmitter code (UART_write) sets the parity output port first and then writes the 
actual data. The receiver code (UART_read) captures the received parity as part of the 
polling of the FIFO status bits. It then reads the data, computes parity and compares this 
with the received bit. The ZERO flag (Z) indicates any parity errors which can then be 
used at the higher level in the program. 

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                    CONSTANT UART_write_port, 10        ;UART Tx 8-bit data output
                    ;
                    CONSTANT UART_control_port, 20      ;UART reset and parity output
                    CONSTANT tx_reset, 01               ;  Tx Buffer Reset - bit0
                    CONSTANT rx_reset, 02               ;  Rx Buffer Reset - bit1
                    CONSTANT tx_parity, 80              ;        Tx Parity - bit7
                    ;
                    CONSTANT UART_status_port, 00       ;Communications status input
                    CONSTANT tx_half_full, 01           ;  Transmitter          half full - bit0
                    CONSTANT tx_full, 02                ;    UART FIFO               full - bit1
                    CONSTANT rx_data_present, 04        ;  Receiver          data present - bit2
                    CONSTANT rx_half_full, 08           ;    UART FIFO          half full - bit3
                    CONSTANT rx_full, 10                ;                            full - bit4
                    CONSTANT status_nul5, 20            ;                          unused - bit5
                    CONSTANT status_nul6, 40            ;                          unused - bit6
                    CONSTANT rx_parity, 80              ;    Parity Bit            parity - bit7
                    ;
                    CONSTANT UART_read_port, 01         ;UART Rx 8-bit data input
                    ;

                    NAMEREG sF, UART_data               ;used for main 8-bit UART data
                    NAMEREG sE, UART_status             ;used for UART status and control
                    ;

                    ;
                    ;Write byte to UART with EVEN or ODD parity.
                    ;
                    ;Data should be provided in register 'UART_data'
                    ;
                    ;Odd and even Parity is describes the total number of 1's sent
                    ;in the complete 9-bit packet formed of 8-bit data and the parity bit.
                    ;For EVEN parity comment out the line indicated ***.
                    ;For ODD parity include the line indicated ***.
                    ;
                    ;Registers used s0, UART_data and UART_status
                    ;
        UART_write: INPUT UART_status, UART_status_port
                    TEST UART_status, tx_full           ;test for space in buffer
                    JUMP NZ, UART_write                 ;wait if no space
                    LOAD s0, 00                         ;compute parity for data being sent
                    TEST UART_data, FF
                    SRA s0                              ;move parity value into MSB
                    XOR s0, 80                          ;**** include this line for ODD parity
                    OUTPUT s0, UART_control_port        ;send parity to UART (no reset)
                    OUTPUT UART_data, UART_write_port   ;write data and parity into transmitter
                    RETURN
                    ;


                    ;Read byte from UART with test for EVEN or ODD parity.
                    ;
                    ;The routine tests and waits for available data and then reads the byte
                    ;data into  register 'UART_data'. The data is then tested against the parity
                    ;bit received. For good data the ZERO flag will be set. A parity error will
                    ;will be signified by the ZERO flag being reset.
                    ;
                    ;Odd and even Parity is describes the total number of 1's sent
                    ;in the complete 9-bit packet formed of 8-bit data and the parity bit.
                    ;For EVEN parity comment out the line indicated ***.
                    ;For ODD parity include the line indicated ***.
                    ;
                    ;Registers used s0, UART_data and UART_status
                    ;
                    ;
         UART_read: INPUT UART_status, UART_status_port ;Test for available character
                    TEST UART_status, rx_data_present   ;test for space in buffer
                    INPUT UART_data, UART_read_port
                    LOAD s0, 00                         ;compute parity for received data
                    TEST UART_data, FF
                    SRA s0
                    XOR s0, 80                          ;****include this line for ODD parity
                    AND UART_status, rx_parity          ;isolate parity bit received
                    XOR s0, UART_status                 ;ZERO set if parity matches
                    RETURN
                    ;

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Simple Error Correction Technique
---------------------------------

This is a very old technique which can provide a degree of error correction. Although a 
parity error can indicate that an error has occurred, it is not possible to know which bit 
has been received in error. This technique can be used to detect and correct the occasional 
bit error. 

In this example we assume that 8 bytes of data are to be sent. These are the ASCII characters
ABCDEFGH. First each byte is transmitted with ODD parity (although EVEN could also be used).

A    0 1 0 0 0 0 0 1   1
B    0 1 0 0 0 0 1 0   1
C    0 1 0 0 0 0 1 1   0
D    0 1 0 0 0 1 0 0   1
E    0 1 0 0 0 1 0 1   0
F    0 1 0 0 0 1 1 0   0
G    0 1 0 0 0 1 1 1   1
H    0 1 0 0 0 1 0 0   1

Next a 'parity byte' is transmitted. Each bit represents the ODD parity of the corresponding bit 
transmitted in the last 8 bytes. In other words, it is the ODD parity associated with each of 
the above columns.

     1 1 1 1 1 0 1 1   *

It is debatable as to what to transmit as parity for this 'parity byte'. It could just be the 
parity of the 'parity byte' in the normal way. It could be the parity of the previous 8 parity 
bits transmitted or a combination of both. The uart9 macros allow you to make the choice in 
software because it is treated the same way as any other data bit.


Now consider receiving the above data packet, but with a bit error at bit 6 of the character 'D'.

A    0 1 0 0 0 0 0 1   1
B    0 1 0 0 0 0 1 0   1
C    0 1 0 0 0 0 1 1   0
D    0 0 0 0 0 1 0 0   1   <----- Parity error
E    0 1 0 0 0 1 0 1   0
F    0 1 0 0 0 1 1 0   0
G    0 1 0 0 0 1 1 1   1
H    0 1 0 0 0 1 0 0   1
     1 1 1 1 1 0 1 1   *

       ^
       |
     parity
     error

The parity error on the 'D' line tells us there has been some kind of error but we do not know 
which bit caused it. The 'parity byte' also indicates that an error has occurred in the bit 6 
column, but we don't know which byte was the cause. However, it can easily be seen that the 
intersection of these error points reveals the bit error and it would therefore be reasonable 
to correct this bit by simple inversion.

It is possible to correct more than one bit error in a packet so long as the errors occur in 
different rows and columns. There is always a danger that the parity bits may be corrupted and 
this is where the parity of the 'parity byte' (*) could benefit from being the computation of
all 16 parity bits.

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End of file UART9_readme.txt
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