uart9_readme.txt

This the 8th release of PicoBlaze for Spartan-3, Spartan-3E Virtex-II, Virtex-IIPro and Virtex-4 d

UART9 readme.txt

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9-Bit UART Macros with Integral FIFO Buffers.
Suitable for communication with Parity.


Release 1 - 3rd March 2005




Author
------

Ken Chapman
Staff Engineer - Spartan Applications Specialist
Xilinx Ltd (UK)

email: [e-mail]


Introduction
------------

These macros have been supplied to complement the standard 8-bit UART macros supplied with PicoBlaze. 
You are advised to look at the standard macros and documentation (UART_manual.pdf) first as these 
variants take almost the same format and must be used and controlled in the same fundamental way.

The UART9 macros provide a UART which has 1 start bit, 9 data bits and 1 stop bit. 
The additional data bit can be used to provide different functionality depending on the way you 
choose to interpret it. 

Transmitter macro is called 'uart9_tx.vhd' and the additional bit is data_in(8).
Receiver macro is called 'uart9_rx.vhd' and the additional bit is data_out(8).

Parity - Drive data_in(8) with a High or Low depending on the state or the remaining data bits
         data_in(7 downto 0) and the desired ODD or EVEN parity.
         Interpret and check the received data_out(8) as required by your application.

Data - The additional bit can be used as an additional data bit.

Stop bit - Forcing a High and checking for High allows the UART to provide 1 start bit, 8 data 
           bits and 2 stop bits format.


Is Parity Required?
-------------------

The most common reason for the 9th bit is to provide support for parity. Before choosing to 
implement parity in a system you should ask the fundamental question "Do I really need it?".
To help answer that question, you need to consider what your system will do if a parity error
should occur. Will it just ignore an error and what will be the effect if it does? If it 
does not ignore the error, then what will it do? All of these factors will need to be solved 
at a higher level than these macros and PicoBlaze will almost certainly provide a suitable 
platform in which to implement this protocol.

In many cases the need for parity is simply to enable connection to another piece of equipment 
which expects parity and which can not be changed. It is not unusual in these cases for the received 
parity to be ignored or for incorrect data to be discarded with unpredictable results. Fortunately 
most serial connections such as RS232 are now very reliable once initial communication has 
been established.



Using the Macros 
----------------

The macros are provided as source VHDL and should be instantiated in your design. Each macro 
also uses two sub macros and therefore these files must also be added to the project.

uart9_tx
   |
   |__kcuart9_tx
   |
   |__bbfifo_16x9


uart9_rx
   |
   |__kcuart9_rx
   |
   |__bbfifo_16x9


The instantiation templates are exactly the same as those required for the standard 8-bit 
macros except that the data bus in each case is now 9 bits. 


Component declaration........

----------------------------------------------------------------------------------------

  component uart9_tx
    Port (            data_in : in std_logic_vector(8 downto 0);
                 write_buffer : in std_logic;
                 reset_buffer : in std_logic;
                 en_16_x_baud : in std_logic;
                   serial_out : out std_logic;
                  buffer_full : out std_logic;
             buffer_half_full : out std_logic;
                          clk : in std_logic);
    end component;


  component uart9_rx
    Port (            serial_in : in std_logic;
                       data_out : out std_logic_vector(8 downto 0);
                    read_buffer : in std_logic;
                   reset_buffer : in std_logic;
                   en_16_x_baud : in std_logic;
            buffer_data_present : out std_logic;
                    buffer_full : out std_logic;
               buffer_half_full : out std_logic;
                            clk : in std_logic);
  end component;


----------------------------------------------------------------------------------------

Component Instantiation......

Signal names will probably change to fit with your design.

----------------------------------------------------------------------------------------

  transmit: uart9_tx 
  port map (            data_in => data_in, 
                   write_buffer => write_buffer,
                   reset_buffer => reset_buffer,
                   en_16_x_baud => en_16_x_baud,
                     serial_out => serial_out,
                    buffer_full => buffer_full,
               buffer_half_full => buffer_half_full,
                            clk => clk );

  receive: uart9_rx
  port map (            serial_in => serial_in,
                         data_out => data_out
                      read_buffer => read_buffer
                     reset_buffer => reset_buffer,
                     en_16_x_baud => en_16_x_baud,
              buffer_data_present => buffer_data_present,
                      buffer_full => buffer_full,
                 buffer_half_full => buffer_half_full,
                              clk => clk );  


----------------------------------------------------------------------------------------


Providing Parity
----------------

Parity is defined as being ODD or EVEN. The term ODD and EVEN refers to the total number of 
High (1) bits being transmitted including the parity bit itself. 

For example the ASCII code for the letter 'A' is 41 hex. The 8-bit binary representation is 
therefore 01000001 which clearly has an even number of 1's. So the parity bit will High (1) 
for ODD parity and '0' for EVEN parity.  

To transmit parity using the uart9_tx macro, the parity bit needs to be computed and then 
applied along with the 8 data bits when activating the write_buffer control. This could be
achieved in hardware by creating an XOR gate for EVEN parity or an XNOR for ODD parity.

--ODD parity 
data_in(8) <= data_in(0) xor data_in(1) xor data_in(2) xor data_in(3)   
                  xor data_in(4) xor data_in(5) xor data_in(6) xor data_in(7); 

PicoBlaze can also be used to calculate parity and may offer additional flexibility.
Since the ports and operation of PicoBlaze is 8-bits, connections to the uart_tx now 
requires 2 ports. The first port can be used to provide the parity bit which will then 
be held in a register. Then when the second port writes the main 8-bit data directly 
into the FIFO buffer the parity bit is combined to form the complete 9-bit value. By 
careful design the spare bits of the port used to set the parity bits can also be used
for control the reset on the UART FIFO buffers if required.

When receiving data, hardware logic could again be used to compute the parity of the data
and compare this with the received parity bit (XNOR gate). This would result in a 
'parity error' flag which the associated processor would still need to read. So unless 
the processor is really very occupied, it is probably easier and more efficient to read 
the parity bit directly and perform the error test in software. 


----------------------------------------------------------------------------------------

PicoBlaze interface to uart9_tx and uart_rx supporting parity.  

The following sections of code describe a potential interface between PicoBlaze and the 
uart9 macros. Notice how the FIFO buffers are fully controlled and monitored by the 
Processor and the parity bit is treated as bit7 of allocated input and output ports.    

----------------------------------------------------------------------------------------

signal rx_data             : std_logic_vector(8 downto 0);
signal tx_data             : std_logic_vector(8 downto 0);
signal tx_parity           : std_logic;
signal write_to_uart       : std_logic;
signal tx_full             : std_logic;
signal tx_half_full        : std_logic;
signal read_from_uart      : std_logic;
signal rx_data_present     : std_logic;
signal rx_full             : std_logic;
signal rx_half_full        : std_logic;
signal uart_status         : std_logic_vector(7 downto 0);
signal tx_reset            : std_logic;
signal rx_reset            : std_logic;

...............

  --UART Transmitter interface

  parity_tx_port: process(clk)
  begin

    if clk'event and clk='1' then
      if write_strobe='1' then

        -- PORT 20 : UART FIFO control and transmitter parity.
        if port_id(5)='1' then
          tx_reset <= out_port(0);
          rx_reset <= out_port(1);
          tx_parity <= out_port(7);
        end if;

      end if;
    end if;