📄 mpeg2.rpt
字号:
E8 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 10/22( 45%)
E9 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 14/22( 63%)
E10 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 1/2 0/2 3/22( 13%)
E11 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 13/22( 59%)
E12 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 1/2 0/2 3/22( 13%)
E14 5/ 8( 62%) 4/ 8( 50%) 0/ 8( 0%) 1/2 0/2 9/22( 40%)
E15 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 2/2 0/2 6/22( 27%)
E16 4/ 8( 50%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 6/22( 27%)
E18 5/ 8( 62%) 2/ 8( 25%) 3/ 8( 37%) 2/2 0/2 5/22( 22%)
E20 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 1/2 0/2 2/22( 9%)
E22 7/ 8( 87%) 0/ 8( 0%) 5/ 8( 62%) 2/2 0/2 8/22( 36%)
E23 3/ 8( 37%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 2/22( 9%)
F1 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 1/2 0/2 8/22( 36%)
F2 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 1/2 0/2 8/22( 36%)
F3 4/ 8( 50%) 3/ 8( 37%) 1/ 8( 12%) 1/2 0/2 9/22( 40%)
F4 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 5/22( 22%)
F5 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 1/2 0/2 2/22( 9%)
F6 4/ 8( 50%) 1/ 8( 12%) 3/ 8( 37%) 2/2 1/2 5/22( 22%)
F7 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 3/22( 13%)
F8 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 10/22( 45%)
F9 2/ 8( 25%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 3/22( 13%)
F10 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 2/2 0/2 10/22( 45%)
F11 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 2/2 0/2 9/22( 40%)
F12 3/ 8( 37%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 1/22( 4%)
F13 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 12/22( 54%)
F14 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 1/2 0/2 1/22( 4%)
F15 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 2/2 0/2 8/22( 36%)
F16 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 1/2 0/2 1/22( 4%)
F17 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
F18 3/ 8( 37%) 1/ 8( 12%) 2/ 8( 25%) 2/2 0/2 4/22( 18%)
F19 6/ 8( 75%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 7/22( 31%)
F20 4/ 8( 50%) 3/ 8( 37%) 0/ 8( 0%) 2/2 0/2 3/22( 13%)
F21 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 2/2 0/2 9/22( 40%)
F23 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 1/2 0/2 11/22( 50%)
F24 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 7/22( 31%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 141/141 (100%)
Total logic cells used: 771/1152 ( 66%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 2.29/4 ( 57%)
Total fan-in: 1770/4608 ( 38%)
Total input pins required: 56
Total input I/O cell registers required: 0
Total output pins required: 90
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 1
Total reserved pins required 0
Total logic cells required: 771
Total flipflops required: 444
Total packed registers required: 0
Total logic cells in carry chains: 109
Total number of carry chains: 11
Total number of carry chains of length 1-8 : 5
Total number of carry chains of length 9-16: 5
Total number of carry chains of length 17-24: 1
Total logic cells in cascade chains: 42
Total number of cascade chains: 18
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 228/1152 ( 19%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 2 4 4 8 8 8 8 8 7 8 8 8 0 0 0 8 3 3 3 7 0 0 8 8 5 126/0
B: 0 5 8 7 8 0 8 0 7 6 8 8 0 1 8 8 8 2 8 8 0 0 8 8 7 131/0
C: 7 0 8 6 3 8 5 8 7 6 6 4 0 6 8 4 1 8 0 0 0 6 8 7 0 116/0
D: 2 6 8 8 6 8 8 4 8 2 3 3 0 8 8 6 2 7 7 8 5 6 8 6 2 139/0
E: 8 5 0 8 8 0 8 8 8 8 8 8 0 0 5 8 4 0 5 0 8 0 7 3 0 117/0
F: 8 8 4 8 8 4 2 8 2 8 8 3 0 8 8 8 8 2 3 6 4 8 0 8 8 142/0
Total: 27 28 32 45 41 28 39 36 39 38 41 34 0 23 37 42 26 22 26 29 17 20 39 40 22 771/0
Device-Specific Information: d:\mpeg2-8m\070531\mpeg2.rpt
mpeg2
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
17 - - C -- INPUT 0 0 0 1 A_OUT
15 - - B -- INPUT 0 0 0 1 AOUT0
14 - - B -- INPUT 0 0 0 1 AOUT1
12 - - B -- INPUT 0 0 0 1 AOUT2
10 - - A -- INPUT 0 0 0 1 AOUT3
8 - - A -- INPUT 0 0 0 1 AOUT4
9 - - A -- INPUT 0 0 0 1 AOUT5
11 - - B -- INPUT 0 0 0 1 AOUT6
13 - - B -- INPUT 0 0 0 1 AOUT7
168 - - - 06 INPUT 0 0 0 24 A10
167 - - - 05 INPUT 0 0 0 24 A11
172 - - - 08 INPUT 0 0 0 24 A12
169 - - - 06 INPUT 0 0 0 11 A13
170 - - - 07 INPUT 0 0 0 11 A14
173 - - - 09 INPUT 0 0 0 11 A15
36 - - E -- INPUT 0 0 0 1 CHANGE
161 - - - 02 INPUT 0 0 0 65 CK2M
160 - - - 02 INPUT 0 0 0 13 CK4M
183 - - - -- INPUT G 0 0 0 1 CK8M
79 - - - -- INPUT 0 0 0 0 CK16M
176 - - - 11 BIDIR 0 1 0 17 D0
175 - - - 10 INPUT 0 0 0 4 D1
174 - - - 09 INPUT 0 0 0 2 D2
61 - - - 20 INPUT 0 0 0 1 END0
60 - - - 21 INPUT 0 0 0 1 END1
58 - - - 21 INPUT 0 0 0 1 END2
57 - - - 22 INPUT 0 0 0 1 END3
56 - - - 23 INPUT 0 0 0 1 END4
55 - - - 24 INPUT 0 0 0 1 END5
54 - - - 24 INPUT 0 0 0 1 END6
53 - - F -- INPUT 0 0 0 1 END7
47 - - F -- INPUT 0 0 0 1 FIFO_E
162 - - - 03 INPUT 0 0 0 23 FP8STB
163 - - - 03 INPUT 0 0 0 62 FR8
193 - - - 17 INPUT 0 0 0 1 INT1
197 - - - 19 INPUT 0 0 0 1 INT2
202 - - - 21 INPUT 0 0 0 1 INT3
198 - - - 20 INPUT 0 0 0 1 INT4
191 - - - 16 INPUT 0 0 0 1 RCLK1
190 - - - 15 INPUT 0 0 0 1 RCLK2
187 - - - 14 INPUT 0 0 0 1 RCLK3
189 - - - 14 INPUT 0 0 0 1 RCLK4
182 - - - -- INPUT 0 0 0 3 RD/
177 - - - 11 INPUT 0 0 0 9 RSTL
64 - - - 18 INPUT 0 0 0 1 STREQ
136 - - C -- INPUT 0 0 0 1 TD0
140 - - B -- INPUT 0 0 0 1 TD1
142 - - B -- INPUT 0 0 0 1 TD2
144 - - B -- INPUT 0 0 0 1 TD3
147 - - A -- INPUT 0 0 0 1 TD4
143 - - B -- INPUT 0 0 0 1 TD5
141 - - B -- INPUT 0 0 0 1 TD6
139 - - B -- INPUT 0 0 0 1 TD7
135 - - C -- INPUT 0 0 0 1 TEF
78 - - - -- INPUT 0 0 0 5 UHW
184 - - - -- INPUT 0 0 0 18 WR/
80 - - - -- INPUT 0 0 0 1 YUHW
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\mpeg2-8m\070531\mpeg2.rpt
mpeg2
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
203 - - - 22 OUTPUT 0 1 0 0 A_CLK
16 - - C -- OUTPUT 0 1 0 0 A_CSN
204 - - - 23 OUTPUT 0 1 0 0 A_IN
19 - - C -- OUTPUT 0 1 0 0 AIN0
25 - - D -- OUTPUT 0 1 0 0 AIN1
27 - - D -- OUTPUT 0 1 0 0 AIN2
29 - - D -- OUTPUT 0 1 0 0 AIN3
30 - - D -- OUTPUT 0 1 0 0 AIN4
28 - - D -- OUTPUT 0 1 0 0 AIN5
26 - - D -- OUTPUT 0 1 0 0 AIN6
24 - - D -- OUTPUT 0 1 0 0 AIN7
18 - - C -- OUTPUT 0 1 0 0 AUDIO_MR
195 - - - 18 OUTPUT 0 1 0 0 CS1/
196 - - - 18 OUTPUT 0 1 0 0 CS2/
200 - - - 21 OUTPUT 0 1 0 0 CS3/
199 - - - 20 OUTPUT 0 1 0 0 CS4/
192 - - - 16 OUTPUT 0 1 0 0 CS4314/
166 - - - 04 OUTPUT 0 1 0 0 CS6388/
186 - - - 13 OUTPUT 0 1 0 0 C2O2
180 - - - 13 OUTPUT 0 1 0 0 C8O2
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