delay_counter.v

来自「这是实现在4条E1接口上捆绑实现8M传输的逻辑源码」· Verilog 代码 · 共 95 行

module	delay_counter(
						DELAY_A		,
						FIFO_MR			,
						WR_FIFO			,
						RD_FIFO_OE		,
						);
  	input[2:0]			DELAY_A		;
	input			FIFO_MR			;
 	input			WR_FIFO			;
  	output			RD_FIFO_OE		;
	reg[15:0]		COUNT			;
	reg				RD_FIFO_OE		;
	reg				COUNT_OE		;
  always@( posedge WR_FIFO )
        begin
                if ( !FIFO_MR)
                		begin
						COUNT		<=	16'b0;
						RD_FIFO_OE<='B1;
						COUNT_OE<='B1;
                		end 
					else
						begin
								if(COUNT_OE)
                					begin
                  					COUNT<=COUNT+1;
										case( DELAY_A )
                                  		3'b000: 	begin
												if(COUNT=='H0C00)
                									begin
                  									COUNT_OE<='B0;
													RD_FIFO_OE<='B0;
													end
                                        		end
                                  		3'b001: 	begin
												if(COUNT=='H1900)
                									begin
                  									COUNT_OE<='B0;
													RD_FIFO_OE<='B0;
													end
                                         		end
                                  		3'b010: 	begin
												if(COUNT=='H1e00)
                									begin
                  									COUNT_OE<='B0;
													RD_FIFO_OE<='B0;
													end
                                        		end
                                  		3'b011: 	begin
												if(COUNT=='H2400)
                									begin
                  									COUNT_OE<='B0;
													RD_FIFO_OE<='B0;
													end
                                        		end
                                  		3'b100: 	begin
												if(COUNT=='H2a00)
                									begin
                  									COUNT_OE<='B0;
													RD_FIFO_OE<='B0;
													end
                                        		end
                                  		3'b101: 	begin
												if(COUNT=='H3700)
                									begin
                  									COUNT_OE<='B0;
													RD_FIFO_OE<='B0;
													end
                                        		end
                                  		3'b110: 	begin
												if(COUNT=='H3D00)
                									begin
                  									COUNT_OE<='B0;
													RD_FIFO_OE<='B0;
													end
                                        		end
                                  		3'b111: 	begin
												if(COUNT=='H2000)
                									begin
                  									COUNT_OE<='B0;
													RD_FIFO_OE<='B0;
													end
                                        		end
										endcase

									end
								else
									begin
									RD_FIFO_OE<='B0;
									end
                        end
		end
endmodule