mpeg2.acf

这是实现在4条E1接口上捆绑实现8M传输的逻辑源码

--
--  Copyright (C) 1988-2002 Altera Corporation
--  Any megafunction design, and related net list (encrypted or decrypted),
--  support information, device programming or simulation file, and any other
--  associated documentation or information provided by Altera or a partner
--  under Altera's Megafunction Partnership Program may be used only to
--  program PLD devices (but not masked PLD devices) from Altera.  Any other
--  use of such megafunction design, net list, support information, device
--  programming or simulation file, or any other related documentation or
--  information is prohibited for any other purpose, including, but not
--  limited to modification, reverse engineering, de-compiling, or use with
--  any other silicon devices, unless such use is explicitly licensed under
--  a separate agreement with Altera or a megafunction partner.  Title to
--  the intellectual property, including patents, copyrights, trademarks,
--  trade secrets, or maskworks, embodied in any such megafunction design,
--  net list, support information, device programming or simulation file, or
--  any other related documentation or information provided by Altera or a
--  megafunction partner, remains with Altera, the megafunction partner, or
--  their respective licensors.  No other licenses, including any licenses
--  needed under any third party's intellectual property, are provided herein.
--
CHIP mpeg2
BEGIN
	|YDHW :	OUTPUT_PIN = 208;
	|Y2M :	OUTPUT_PIN = 207;
	|YTS :	OUTPUT_PIN = 206;
	|RSTL_3V :	OUTPUT_PIN = 205;
	|A_IN :	OUTPUT_PIN = 204;
	|A_CLK :	OUTPUT_PIN = 203;
	|WR/ :	INPUT_PIN = 184;
	|RD/ :	INPUT_PIN = 182;
	|F8O2 :	OUTPUT_PIN = 179;
	|RSTL :	INPUT_PIN = 177;
	|RSTH :	OUTPUT_PIN = 157;
	|RRD :	OUTPUT_PIN = 150;
	|FIFO_OE :	OUTPUT_PIN = 149;
	|RD_DFIFO :	OUTPUT_PIN = 148;
	|TEF :	INPUT_PIN = 135;
	|TWR :	OUTPUT_PIN = 126;
	|RWR :	OUTPUT_PIN = 121;
	|W4 :	OUTPUT_PIN = 120;
	|R4 :	OUTPUT_PIN = 119;
	|R3 :	OUTPUT_PIN = 113;
	|W3 :	OUTPUT_PIN = 114;
	|W2 :	OUTPUT_PIN = 104;
	|R2 :	OUTPUT_PIN = 103;
	|W1 :	OUTPUT_PIN = 99;
	|YUHW :	INPUT_PIN = 80;
	|UHW :	INPUT_PIN = 78;
	|W_AFIFO :	OUTPUT_PIN = 31;
	|AUDIO_MR :	OUTPUT_PIN = 18;
	|A_CSN :	OUTPUT_PIN = 16;
	|R1 :	OUTPUT_PIN = 100;
	|INTS :	OUTPUT_PIN = 158;
	|RELAY7 :	OUTPUT_PIN = 37;
	|RELAY6 :	OUTPUT_PIN = 38;
	|RELAY5 :	OUTPUT_PIN = 39;
	|RELAY4 :	OUTPUT_PIN = 40;
	|RELAY2 :	OUTPUT_PIN = 44;
	|RELAY1 :	OUTPUT_PIN = 45;
	|RELAY0 :	OUTPUT_PIN = 46;
	|RD3 :	OUTPUT_PIN = 125;
	|RD4 :	OUTPUT_PIN = 122;
	|RD5 :	OUTPUT_PIN = 127;
	|RD2 :	OUTPUT_PIN = 128;
	|RD6 :	OUTPUT_PIN = 131;
	|RD1 :	OUTPUT_PIN = 132;
	|RD7 :	OUTPUT_PIN = 133;
	|RD0 :	OUTPUT_PIN = 134;
	|RCLK :	OUTPUT_PIN = 159;
	|OE5 :	OUTPUT_PIN = 69;
	|OE4 :	OUTPUT_PIN = 115;
	|OE3 :	OUTPUT_PIN = 111;
	|OE2 :	OUTPUT_PIN = 101;
	|OE1 :	OUTPUT_PIN = 87;
	|MR4 :	OUTPUT_PIN = 116;
	|MR3 :	OUTPUT_PIN = 112;
	|MR2 :	OUTPUT_PIN = 102;
	|MR1 :	OUTPUT_PIN = 97;
	|IIC_A2 :	OUTPUT_PIN = 65;
	|IIC_A1 :	OUTPUT_PIN = 67;
	|IIC_A0 :	OUTPUT_PIN = 68;
	|FD0 :	OUTPUT_PIN = 86;
	|FD1 :	OUTPUT_PIN = 85;
	|FD2 :	OUTPUT_PIN = 83;
	|FD3 :	OUTPUT_PIN = 75;
	|FD4 :	OUTPUT_PIN = 74;
	|FD5 :	OUTPUT_PIN = 73;
	|FD6 :	OUTPUT_PIN = 71;
	|FD7 :	OUTPUT_PIN = 70;
	|VD4 :	OUTPUT_PIN = 88;
	|VD3 :	OUTPUT_PIN = 89;
	|VD5 :	OUTPUT_PIN = 90;
	|VD2 :	OUTPUT_PIN = 92;
	|VD6 :	OUTPUT_PIN = 93;
	|VD1 :	OUTPUT_PIN = 94;
	|VD7 :	OUTPUT_PIN = 95;
	|VD0 :	OUTPUT_PIN = 96;
	|DHW :	OUTPUT_PIN = 164;
	|DESTEN :	OUTPUT_PIN = 63;
	|ENSTEN :	OUTPUT_PIN = 62;
	|CS6388/ :	OUTPUT_PIN = 166;
	|C8O2 :	OUTPUT_PIN = 180;
	|C2O2 :	OUTPUT_PIN = 186;
	|CS4314/ :	OUTPUT_PIN = 192;
	|CS4/ :	OUTPUT_PIN = 199;
	|CS3/ :	OUTPUT_PIN = 200;
	|CS2/ :	OUTPUT_PIN = 196;
	|CS1/ :	OUTPUT_PIN = 195;
	|AIN0 :	OUTPUT_PIN = 19;
	|AIN4 :	OUTPUT_PIN = 30;
	|AIN3 :	OUTPUT_PIN = 29;
	|AIN5 :	OUTPUT_PIN = 28;
	|AIN2 :	OUTPUT_PIN = 27;
	|AIN6 :	OUTPUT_PIN = 26;
	|AIN1 :	OUTPUT_PIN = 25;
	|TD4 :	INPUT_PIN = 147;
	|TD3 :	INPUT_PIN = 144;
	|TD5 :	INPUT_PIN = 143;
	|TD2 :	INPUT_PIN = 142;
	|TD6 :	INPUT_PIN = 141;
	|TD1 :	INPUT_PIN = 140;
	|TD7 :	INPUT_PIN = 139;
	|TD0 :	INPUT_PIN = 136;
	|STREQ :	INPUT_PIN = 64;
	|RCLK4 :	INPUT_PIN = 189;
	|RCLK3 :	INPUT_PIN = 187;
	|RCLK2 :	INPUT_PIN = 190;
	|RCLK1 :	INPUT_PIN = 191;
	|INT3 :	INPUT_PIN = 202;
	|INT4 :	INPUT_PIN = 198;
	|INT2 :	INPUT_PIN = 197;
	|INT1 :	INPUT_PIN = 193;
	|FR8 :	INPUT_PIN = 163;
	|FP8STB :	INPUT_PIN = 162;
	|FIFO_E :	INPUT_PIN = 47;
	|END7 :	INPUT_PIN = 53;
	|END6 :	INPUT_PIN = 54;
	|END5 :	INPUT_PIN = 55;
	|END4 :	INPUT_PIN = 56;
	|END3 :	INPUT_PIN = 57;
	|END2 :	INPUT_PIN = 58;
	|END1 :	INPUT_PIN = 60;
	|END0 :	INPUT_PIN = 61;
	|D0 :	BIDIR_PIN = 176;
	|D2 :	INPUT_PIN = 174;
	|D1 :	INPUT_PIN = 175;
	|CK16M :	INPUT_PIN = 79;
	|CK8M :	INPUT_PIN = 183;
	|CK4M :	INPUT_PIN = 160;
	|CK2M :	INPUT_PIN = 161;
	|CHANGE :	INPUT_PIN = 36;
	|A_OUT :	INPUT_PIN = 17;
	|A15 :	INPUT_PIN = 173;
	|A14 :	INPUT_PIN = 170;
	|A13 :	INPUT_PIN = 169;
	|A12 :	INPUT_PIN = 172;
	|A11 :	INPUT_PIN = 167;
	|A10 :	INPUT_PIN = 168;
	|AIN7 :	OUTPUT_PIN = 24;
	|AOUT0 :	INPUT_PIN = 15;
	|AOUT1 :	INPUT_PIN = 14;
	|AOUT7 :	INPUT_PIN = 13;
	|AOUT2 :	INPUT_PIN = 12;
	|AOUT6 :	INPUT_PIN = 11;
	|AOUT3 :	INPUT_PIN = 10;
	|AOUT5 :	INPUT_PIN = 9;
	|AOUT4 :	INPUT_PIN = 8;
	|RELAY3 :	OUTPUT_PIN = 41;
	|RD_AFIFO :	OUTPUT_PIN = 7;
	DEVICE = EPF10K20RC208-3;
END;

DEFAULT_DEVICES
BEGIN
	AUTO_DEVICE = EPF10K70RC240-2;
	AUTO_DEVICE = EPF10K30BC356-3;
	AUTO_DEVICE = EPF10K30RC240-3;
	AUTO_DEVICE = EPF10K30RC208-3;
	AUTO_DEVICE = EPF10K20RC240-3;
	AUTO_DEVICE = EPF10K20RC208-3;
	AUTO_DEVICE = EPF10K20TC144-3;
	AUTO_DEVICE = EPF10K10QC208-3;
	AUTO_DEVICE = EPF10K10TC144-3;
	AUTO_DEVICE = EPF10K10LC84-3;
	ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
END;

TIMING_POINT
BEGIN
	CUT_ALL_CLEAR_PRESET = ON;
	CUT_ALL_BIDIR = ON;
	DEVICE_FOR_TIMING_SYNTHESIS = EPF10K20RC208-4;
	MAINTAIN_STABLE_SYNTHESIS = ON;
END;

IGNORED_ASSIGNMENTS
BEGIN
	DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
	IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF;
	IGNORE_DEVICE_ASSIGNMENTS = OFF;
	IGNORE_LC_ASSIGNMENTS = OFF;
	IGNORE_PIN_ASSIGNMENTS = OFF;
	IGNORE_CHIP_ASSIGNMENTS = OFF;
	IGNORE_TIMING_ASSIGNMENTS = OFF;
	IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
	IGNORE_CLIQUE_ASSIGNMENTS = OFF;
	FIT_IGNORE_TIMING = OFF;
END;

GLOBAL_PROJECT_DEVICE_OPTIONS
BEGIN
	FLEX_CONFIGURATION_EPROM = EPC1PC8;
	FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
	FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON;
	FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
	FLEX6000_ENABLE_JTAG = OFF;
	CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL;
	MULTIVOLT_IO = OFF;
	MAX7000S_ENABLE_JTAG = ON;
	FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
	MAX7000S_USER_CODE = FFFF;
	CONFIG_SCHEME_10K = PASSIVE_SERIAL;
	FLEX10K_JTAG_USER_CODE = 7F;
	ENABLE_INIT_DONE_OUTPUT = OFF;
	ENABLE_CHIP_WIDE_OE = OFF;
	ENABLE_CHIP_WIDE_RESET = OFF;
	nCEO = UNRESERVED;
	CLKUSR = UNRESERVED;
	ADD17 = UNRESERVED;
	ADD16 = UNRESERVED;
	ADD15 = UNRESERVED;
	ADD14 = UNRESERVED;
	ADD13 = UNRESERVED;
	ADD0_TO_ADD12 = UNRESERVED;
	SDOUT = RESERVED_DRIVES_OUT;
	RDCLK = UNRESERVED;
	RDYnBUSY = UNRESERVED;
	nWS_nRS_nCS_CS = UNRESERVED;
	DATA1_TO_DATA7 = UNRESERVED;
	DATA0 = RESERVED_TRI_STATED;
	FLEX8000_ENABLE_JTAG = OFF;
	CONFIG_SCHEME = ACTIVE_SERIAL;
	DISABLE_TIME_OUT = OFF;
	ENABLE_DCLK_OUTPUT = OFF;
	RELEASE_CLEARS = OFF;
	AUTO_RESTART = OFF;
	USER_CLOCK = OFF;
	SECURITY_BIT = OFF;
	RESERVED_PINS_PERCENT = 0;
	RESERVED_LCELLS_PERCENT = 0;
	MAX7000AE_USER_CODE = FFFFFFFF;
	MAX7000AE_ENABLE_JTAG = ON;
	CONFIG_EPROM_USER_CODE = FFFFFFFF;
	CONFIG_EPROM_PULLUP_RESISTOR = ON;
	MAX7000B_VCCIO_IOBANK1 = 3.3V;
	MAX7000B_VCCIO_IOBANK2 = 3.3V;
	MAX7000B_ENABLE_VREFA = OFF;
	MAX7000B_ENABLE_VREFB = OFF;
END;

GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
BEGIN
	STYLE = FAST;
	MULTI_LEVEL_SYNTHESIS_MAX9000 = ON;
	AUTO_IMPLEMENT_IN_EAB = OFF;
	AUTO_OPEN_DRAIN_PINS = ON;
	ONE_HOT_STATE_MACHINE_ENCODING = OFF;
	AUTO_REGISTER_PACKING = OFF;
	DEVICE_FAMILY = FLEX10K;
	AUTO_FAST_IO = OFF;
	AUTO_GLOBAL_OE = ON;
	AUTO_GLOBAL_PRESET = ON;
	AUTO_GLOBAL_CLEAR = ON;
	AUTO_GLOBAL_CLOCK = ON;
	MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF;
	OPTIMIZE_FOR_SPEED = 5;
END;

COMPILER_PROCESSING_CONFIGURATION
BEGIN
	PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF;
	FITTER_SETTINGS = NORMAL;
	SMART_RECOMPILE = OFF;
	GENERATE_AHDL_TDO_FILE = OFF;
	RPT_FILE_USER_ASSIGNMENTS = ON;
	RPT_FILE_LCELL_INTERCONNECT = ON;
	RPT_FILE_HIERARCHY = ON;
	RPT_FILE_EQUATIONS = ON;
	LINKED_SNF_EXTRACTOR = OFF;
	OPTIMIZE_TIMING_SNF = OFF;
	TIMING_SNF_EXTRACTOR = ON;
	FUNCTIONAL_SNF_EXTRACTOR = OFF;
	DESIGN_DOCTOR_RULES = EPLD;
	DESIGN_DOCTOR = OFF;
END;

COMPILER_INTERFACES_CONFIGURATION
BEGIN
	USE_ADT_PALACE_FOR_MAX = OFF;
	VHDL_WRITER_VERSION = VHDL87;
	VHDL_READER_VERSION = VHDL87;
	SYNOPSYS_MAPPING_EFFORT = MEDIUM;
	SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
	SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
	SYNOPSYS_DESIGNWARE = OFF;
	SYNOPSYS_COMPILER = DESIGN;
	USE_SYNOPSYS_SYNTHESIS = OFF;
	VHDL_NETLIST_WRITER = OFF;
	VERILOG_NETLIST_WRITER = OFF;
	XNF_GENERATE_AHDL_TDX_FILE = ON;
	XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
	XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
	EDIF_OUTPUT_VERSION = 200;
	EDIF_NETLIST_WRITER = OFF;
	VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
	VERILOG_TRUNCATE_HIERARCHY_PATH = OFF;
	VHDL_TRUNCATE_HIERARCHY_PATH = OFF;
	EDIF_TRUNCATE_HIERARCHY_PATH = OFF;
	VERILOG_FLATTEN_BUS = OFF;
	VHDL_FLATTEN_BUS = OFF;
	VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE;
	VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE;
	VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF;
	EDIF_INPUT_LMF1 = *.lmf;
	EDIF_INPUT_LMF2 = *.lmf;
	EDIF_OUTPUT_EDC_FILE = *.edc;
	EDIF_INPUT_VCC = VCC;
	EDIF_INPUT_GND = GND;
	EDIF_OUTPUT_VCC = VCC;
	EDIF_OUTPUT_GND = GND;
	EDIF_INPUT_USE_LMF1 = OFF;
	EDIF_INPUT_USE_LMF2 = OFF;
	EDIF_OUTPUT_USE_EDC = OFF;
	EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE;
	EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
	EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF;
	EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF;
	EDIF_FLATTEN_BUS = OFF;
	EDIF_BUS_DELIMITERS = [];
	EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF;
	NETLIST_OUTPUT_TIME_SCALE = 0.1ns;
END;

CUSTOM_DESIGN_DOCTOR_RULES
BEGIN
	MASTER_RESET = OFF;
	EXPANDER_NETWORKS = ON;
	RACE_CONDITIONS = ON;
	DELAY_CHAINS = ON;
	ASYNCHRONOUS_INPUTS = ON;
	PRESET_CLEAR_NETWORKS = ON;
	STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
	STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
	MULTI_CLOCK_NETWORKS = ON;
	MULTI_LEVEL_CLOCKS = ON;
	GATED_CLOCKS = ON;
	RIPPLE_CLOCKS = ON;
END;