mpeg2.tan.qmsg

这是实现在4条E1接口上捆绑实现8M传输的逻辑源码

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CK8M " "Info: Assuming node \"CK8M\" is an undefined clock" {  } { { "mpeg2.gdf" "" { Schematic "D:/mpeg2-8m/070404/mpeg2.gdf" { { 904 376 544 920 "CK8M" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CK8M" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "FR8 " "Info: Assuming node \"FR8\" is an undefined clock" {  } { { "mpeg2.gdf" "" { Schematic "D:/mpeg2-8m/070404/mpeg2.gdf" { { 1128 368 536 1144 "FR8" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "FR8" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "A11 " "Info: Assuming node \"A11\" is an undefined clock" {  } { { "mpeg2.gdf" "" { Schematic "D:/mpeg2-8m/070404/mpeg2.gdf" { { 272 144 312 288 "A11" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "A11" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "A12 " "Info: Assuming node \"A12\" is an undefined clock" {  } { { "mpeg2.gdf" "" { Schematic "D:/mpeg2-8m/070404/mpeg2.gdf" { { 288 144 312 304 "A12" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "A12" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "WR/ " "Info: Assuming node \"WR/\" is an undefined clock" {  } { { "mpeg2.gdf" "" { Schematic "D:/mpeg2-8m/070404/mpeg2.gdf" { { 432 144 312 448 "WR/" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "WR/" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "A14 " "Info: Assuming node \"A14\" is an undefined clock" {  } { { "mpeg2.gdf" "" { Schematic "D:/mpeg2-8m/070404/mpeg2.gdf" { { 320 144 312 336 "A14" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "A14" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "A15 " "Info: Assuming node \"A15\" is an undefined clock" {  } { { "mpeg2.gdf" "" { Schematic "D:/mpeg2-8m/070404/mpeg2.gdf" { { 336 144 312 352 "A15" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "A15" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "A13 " "Info: Assuming node \"A13\" is an undefined clock" {  } { { "mpeg2.gdf" "" { Schematic "D:/mpeg2-8m/070404/mpeg2.gdf" { { 304 144 312 320 "A13" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "A13" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "A10 " "Info: Assuming node \"A10\" is an undefined clock" {  } { { "mpeg2.gdf" "" { Schematic "D:/mpeg2-8m/070404/mpeg2.gdf" { { 256 144 312 272 "A10" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "A10" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "CK2M " "Info: Assuming node \"CK2M\" is an undefined clock" {  } { { "mpeg2.gdf" "" { Schematic "D:/mpeg2-8m/070404/mpeg2.gdf" { { 856 376 544 872 "CK2M" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CK2M" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "FP8STB " "Info: Assuming node \"FP8STB\" is an undefined clock" {  } { { "mpeg2.gdf" "" { Schematic "D:/mpeg2-8m/070404/mpeg2.gdf" { { 960 376 544 976 "FP8STB" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "FP8STB" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "CK4M " "Info: Assuming node \"CK4M\" is an undefined clock" {  } { { "mpeg2.gdf" "" { Schematic "D:/mpeg2-8m/070404/mpeg2.gdf" { { 1008 376 544 1024 "CK4M" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CK4M" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}