re_tune.v

来自「这是实现在4条E1接口上捆绑实现8M传输的逻辑源码」· Verilog 代码 · 共 36 行

module	re_tune(
						FP8			,
						STREQ		,
						nRSET		,
						);
  	input			FP8			;
  	input			STREQ		;
  	output			nRSET		;
	reg[11:0]		COUNT		;
	reg				nRSET		;
  always@( posedge FP8 )
        begin
                if ( STREQ)
                		begin
						COUNT		<=	12'b0;
						nRSET		<= 	'b1;
                		end 
					else

                		begin
                  		COUNT<=COUNT+1;
								if(COUNT=='h300)
								begin
								nRSET	<=	'b0;
								COUNT	<=	12'b0;
								end
								else
								begin
								nRSET<='b1;
								end

                        end
		end
endmodule