counter1.v

来自「这是实现在4条E1接口上捆绑实现8M传输的逻辑源码」· Verilog 代码 · 共 34 行

module	counter1(
						FP8			,
						VD_FLAG		,
						COUT		,
						);
  	input			FP8			;
 	input			VD_FLAG		;
  	output			COUT		;
	reg[11:0]		COUNT		;
	reg				COUT		;
  always@( posedge FP8 or negedge VD_FLAG )
        begin
                if ( VD_FLAG)
                		begin
						COUNT		<=	12'b0;
                		end 
					else

                		begin
                  		COUNT<=COUNT+1;
								if(COUNT=='h200)
								begin
								COUT <='b0;
								end
								else
								begin
								COUT <='b1;
								end

                        end
		end
endmodule