ck4567ts.v

来自「这是实现在4条E1接口上捆绑实现8M传输的逻辑源码」· Verilog 代码 · 共 99 行

module	ck4567ts(
						CK8M		,
						FP8			,
						CH1_DCLK	,
						CH2_DCLK	,
						CH3_DCLK	,
						CH4_DCLK	,
						CMP_DCLK    ,
						//FP8O		,																			
						);
  	input			CK8M		;
 	input			FP8			;
  	output			CH1_DCLK	;
  	output			CH2_DCLK	;
  	output			CH3_DCLK	;
  	output			CH4_DCLK	;
  	output			CMP_DCLK	;
  	//output			FP8O		;

  	reg          	CH1_DCLK	;
   	reg          	CH2_DCLK	;
  	reg          	CH3_DCLK	;
  	reg          	CH4_DCLK	;
  	reg          	CMP_DCLK	;
	reg[11:0]		COUNT		;
	reg				FP8O		;
  always@(negedge CK8M)
		begin
		FP8O	<=	FP8;
		end
  always@( posedge CK8M )
        begin
                if ( FP8O)
                		begin
                        CH1_DCLK    <=  1'b1;
                        CH2_DCLK    <=  1'b1;
                        CH3_DCLK    <=  1'b1;
                        CH4_DCLK    <=  1'b1;
                        CMP_DCLK    <=  1'b1;                        
						COUNT		<=	12'b0;
                		end 
					else

                		begin
                  		COUNT<=COUNT+1;
										if( COUNT=='h026 )
                                  			begin
                                            CH1_DCLK      <= 1'b0;
                                        	end
										else
                                  			begin
                                            CH1_DCLK      <= 1'b1;
                                        	end

										if( COUNT=='h02e )
                                  			begin
                                            CH2_DCLK      <= 1'b0;
                                        	end
										else
                                  			begin
                                            CH2_DCLK      <= 1'b1;
                                        	end
										if( COUNT=='h036 )
                                  			begin
                                            CH3_DCLK      <= 1'b0;
                                        	end
										else
                                  			begin
                                            CH3_DCLK      <= 1'b1;
                                        	end
										if( COUNT=='h03e )
                                  			begin
                                            CH4_DCLK      <= 1'b0;
                                        	end
										else
                                  			begin
                                            CH4_DCLK      <= 1'b1;
                                        	end
										if( COUNT=='h040 )
                                  			begin
                                            CMP_DCLK      <= 1'b0;
                                        	end
										else
                                  			begin
                                            CMP_DCLK      <= 1'b1;
                                        	end

                        end
		end


//  assign	EXSCL=(EXSCL0==1'b0)?  1'b0 : 1'bZ;
//  assign	EXSDA=(EXSDA0==1'b0)?  1'b0 : 1'bZ;
//  assign	EXSCL=EXSCL0;
 // assign	EXSDA=(EXSDAR==1'b0)?  EXSDA0 : 1'bZ;

endmodule