sdsdi_rxtx_demoboard.qsf

DVB系统的SDI数据数据传输接口

# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 2.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:58:29  FEBRUARY 10, 2004"
set_global_assignment -name LAST_QUARTUS_VERSION 4.0
set_global_assignment -name VERILOG_FILE ../../source/sdi_transmit/sdi_makeframe.v
set_global_assignment -name VERILOG_FILE ../../source/sdi_transmit/gen_patho.v
set_global_assignment -name VERILOG_FILE ../../source/sdi_transmit/gen_colorbar.v
set_global_assignment -name VERILOG_FILE ../../source/sdi_transmit/pattern_gen.v
set_global_assignment -name VERILOG_FILE ../../source/sdi_transmit/sdi_scrambler.v
set_global_assignment -name VERILOG_FILE ../../source/sdi_transmit/p2s.v
set_global_assignment -name VERILOG_FILE ../../source/sdi_transmit/hdsdi_trsmatch.v
set_global_assignment -name VERILOG_FILE ../../source/sdi_transmit/hdsdi_crc.v
set_global_assignment -name VERILOG_FILE ../../source/sdi_receive/sdi_aligner.v
set_global_assignment -name VERILOG_FILE ../../source/sdi_receive/sdi_descrambler.v
set_global_assignment -name VERILOG_FILE ../../source/sdi_receive/sdsdi_receive.v
set_global_assignment -name VERILOG_FILE ../../source/sdi_receive/hdsdi_extract_ln.v
set_global_assignment -name VERILOG_FILE ../../source/sdi_receive/s2p.v
set_global_assignment -name VERILOG_FILE ../../source/sdi_receive/gxb_rxsample.v
set_global_assignment -name VERILOG_FILE ../../source/demo/sdsdi_io_interface.v
set_global_assignment -name VERILOG_FILE ../../source/demo/fifo_256x20.v
set_global_assignment -name VERILOG_FILE ../../source/demo/sync.v
set_global_assignment -name VERILOG_FILE ../../source/demo/freq_trans.v
set_global_assignment -name VERILOG_FILE ./sclk_pll_x50_4.v
set_global_assignment -name VERILOG_FILE ../../source/demo/sclk_pll_x30_4.v
set_global_assignment -name VERILOG_FILE ../../source/demo/sclk_pll_x10.v
set_global_assignment -name VERILOG_FILE ../../source/demo/sdsdi_rxtx.v
set_global_assignment -name VERILOG_FILE ../../source/demoboard/sdsdi_rxtx_demoboard.v
set_global_assignment -name SIGNALTAP_FILE debug.stp

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_AG16 -to spare_clk
set_location_assignment PIN_P11 -to asi_led\[0\]
set_location_assignment PIN_R11 -to asi_led\[1\]
set_location_assignment PIN_M12 -to asi_led\[2\]
set_location_assignment PIN_R12 -to asi_led\[3\]
set_location_assignment PIN_AC31 -to sma_rx
set_location_assignment LC_X2_Y15_N0 -to "sdsdi_rxtx:u_demo\|sdsdi_io_interface:u_io_interface\|s2p:u_s2p\|sample_a\[0\]"
set_location_assignment LC_X3_Y15_N0 -to "sdsdi_rxtx:u_demo\|sdsdi_io_interface:u_io_interface\|s2p:u_s2p\|sample_b\[0\]"
set_location_assignment LC_X2_Y15_N1 -to "sdsdi_rxtx:u_demo\|sdsdi_io_interface:u_io_interface\|s2p:u_s2p\|sample_c\[0\]"
set_location_assignment LC_X3_Y15_N1 -to "sdsdi_rxtx:u_demo\|sdsdi_io_interface:u_io_interface\|s2p:u_s2p\|sample_d\[0\]"
set_location_assignment PIN_Y27 -to sma_tx
set_location_assignment PIN_D27 -to button\[0\]
set_location_assignment PIN_F25 -to button\[1\]
set_location_assignment PIN_H23 -to button\[2\]
set_location_assignment PIN_F23 -to button\[3\]
set_location_assignment PIN_T31 -to clock_ref
set_location_assignment PIN_C19 -to ext_video_clk
set_location_assignment PIN_D21 -to header\[0\]
set_location_assignment PIN_E23 -to header\[10\]
set_location_assignment PIN_A24 -to header\[11\]
set_location_assignment PIN_B24 -to header\[12\]
set_location_assignment PIN_C24 -to header\[13\]
set_location_assignment PIN_D24 -to header\[14\]
set_location_assignment PIN_A25 -to header\[15\]
set_location_assignment PIN_B25 -to header\[16\]
set_location_assignment PIN_C25 -to header\[17\]
set_location_assignment PIN_A26 -to header\[18\]
set_location_assignment PIN_E25 -to header\[19\]
set_location_assignment PIN_A21 -to header\[1\]
set_location_assignment PIN_A22 -to header\[2\]
set_location_assignment PIN_C22 -to header\[3\]
set_location_assignment PIN_D22 -to header\[4\]
set_location_assignment PIN_B22 -to header\[5\]
set_location_assignment PIN_E22 -to header\[6\]
set_location_assignment PIN_A23 -to header\[7\]
set_location_assignment PIN_B23 -to header\[8\]
set_location_assignment PIN_C23 -to header\[9\]
set_location_assignment PIN_H25 -to ics660_sel\[0\]
set_location_assignment PIN_H24 -to ics660_sel\[1\]
set_location_assignment PIN_H27 -to ics660_sel\[2\]
set_location_assignment PIN_H26 -to ics660_sel\[3\]
set_location_assignment PIN_G25 -to mk2069_clrn
set_location_assignment PIN_M28 -to mk2069_fv\[0\]
set_location_assignment PIN_J25 -to mk2069_fv\[10\]
set_location_assignment PIN_J24 -to mk2069_fv\[11\]
set_location_assignment PIN_M27 -to mk2069_fv\[1\]
set_location_assignment PIN_M26 -to mk2069_fv\[2\]
set_location_assignment PIN_M25 -to mk2069_fv\[3\]
set_location_assignment PIN_L27 -to mk2069_fv\[4\]
set_location_assignment PIN_L26 -to mk2069_fv\[5\]
set_location_assignment PIN_L25 -to mk2069_fv\[6\]
set_location_assignment PIN_L24 -to mk2069_fv\[7\]
set_location_assignment PIN_K25 -to mk2069_fv\[8\]
set_location_assignment PIN_K24 -to mk2069_fv\[9\]
set_location_assignment PIN_G26 -to mk2069_ld
set_location_assignment PIN_R28 -to mk2069_rv\[0\]
set_location_assignment PIN_N26 -to mk2069_rv\[10\]
set_location_assignment PIN_N25 -to mk2069_rv\[11\]
set_location_assignment PIN_R27 -to mk2069_rv\[1\]
set_location_assignment PIN_P28 -to mk2069_rv\[2\]
set_location_assignment PIN_P27 -to mk2069_rv\[3\]
set_location_assignment PIN_R24 -to mk2069_rv\[4\]
set_location_assignment PIN_P24 -to mk2069_rv\[5\]
set_location_assignment PIN_P26 -to mk2069_rv\[6\]
set_location_assignment PIN_P25 -to mk2069_rv\[7\]
set_location_assignment PIN_N28 -to mk2069_rv\[8\]
set_location_assignment PIN_N27 -to mk2069_rv\[9\]
set_location_assignment PIN_K28 -to mk2069_sv\[0\]
set_location_assignment PIN_L28 -to mk2069_sv\[1\]
set_location_assignment PIN_B18 -to ref27_e
set_location_assignment PIN_AF1 -to refclk2
set_location_assignment PIN_G28 -to refclk2_sel
set_location_assignment PIN_V27 -to rx_clkout
set_location_assignment PIN_K7 -to sdi_led\[0\]
set_location_assignment PIN_L8 -to sdi_led\[1\]
set_location_assignment PIN_H7 -to sdi_led\[2\]
set_location_assignment PIN_L10 -to sdi_led\[3\]
set_location_assignment PIN_N10 -to sdi_led\[4\]
set_location_assignment PIN_M10 -to sdi_led\[5\]
set_location_assignment PIN_M11 -to sdi_led\[6\]
set_location_assignment PIN_P10 -to sdi_led\[7\]
set_location_assignment PIN_R10 -to sdi_rate\[0\]
set_location_assignment PIN_N11 -to sdi_rate\[1\]
set_location_assignment PIN_H1 -to sdi_rx
set_location_assignment PIN_J4 -to sdi_tx
set_location_assignment PIN_E27 -to switch\[0\]
set_location_assignment PIN_F26 -to switch\[1\]
set_location_assignment PIN_J23 -to switch\[2\]
set_location_assignment PIN_K23 -to switch\[3\]
set_location_assignment PIN_B30 -to switch\[4\]
set_location_assignment PIN_M23 -to switch\[5\]
set_location_assignment PIN_C30 -to switch\[6\]
set_location_assignment PIN_F27 -to switch\[7\]
set_location_assignment PIN_G23 -to usr_led\[0\]
set_location_assignment PIN_D28 -to usr_led\[1\]
set_location_assignment PIN_E26 -to usr_led\[2\]
set_location_assignment PIN_G24 -to usr_led\[3\]
set_location_assignment PIN_D29 -to usr_led\[4\]
set_location_assignment PIN_J22 -to usr_led\[5\]
set_location_assignment PIN_L23 -to usr_led\[6\]
set_location_assignment PIN_B31 -to usr_led\[7\]

# Timing Assignments
# ==================
set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP OFF
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name FAMILY "Stratix GX"
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_global_assignment -name TOP_LEVEL_ENTITY sdsdi_rxtx_demoboard
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name AUTO_ENABLE_SMART_COMPILE on

# Fitter Assignments
# ==================
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
set_global_assignment -name AUTO_MERGE_PLLS OFF
set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"