readme.txt

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SD-SDI reference design v1.1 readme.txt

This file contains the following sections:

o  Package Contents
o  Tool Requirements
o  Core Directory Names
o  Release History
o  Contacting Altera

Package Contents
================

SD-SDI reference design v1.1


Tool Requirements
=====================

This reference design requires a Verilog HDL simulator (e.g. Modelsim Altera Edition version 5.7c)

Please contact your local sales representative if you do not have one of these
software tools.


Core Directory Names
====================

The default directory for your reference design is c:\altera\reference_designs,
but you can specify an alternative directory. 


Release History
===============

Version 1.1
-------------

- Update design to use on-board VCXO in loopback mode
- Quartus project support for CVDB rev 1.1 (production version)
- Application note "an356" rev 1.1



Contacting Altera
=================

Although we have made every effort to ensure that this version of the
reference design works correctly, there may be problems that we have 
not encountered. If you have a question or problem that is not answered by 
the information provided in this readme file or the user guide, please contact
your Altera Field Applications Engineer.

If you have additional questions that are not answered in the documentation
provided with this function, contact Altera Applications using one of the
following methods:

Technical Support Hotline:	(800) 800-EPLD (U.S.)
				[phone] (Internationally)
World wide web: 		http://www.altera.com/mysupport

Last updated May, 2004
Copyright