sdsdi_rxtx_cyclone_board.qsf

DVB系统的SDI数据数据传输接口

set_instance_assignment -name IO_STANDARD LVTTL -to header\[1\]
set_instance_assignment -name IO_STANDARD LVTTL -to header\[20\]
set_instance_assignment -name IO_STANDARD LVTTL -to header\[21\]
set_instance_assignment -name IO_STANDARD LVTTL -to header\[22\]
set_instance_assignment -name IO_STANDARD LVTTL -to header\[23\]
set_instance_assignment -name IO_STANDARD LVTTL -to header\[24\]
set_instance_assignment -name IO_STANDARD LVTTL -to header\[25\]
set_instance_assignment -name IO_STANDARD LVTTL -to header\[26\]
set_instance_assignment -name IO_STANDARD LVTTL -to header\[27\]
set_instance_assignment -name IO_STANDARD LVTTL -to header\[28\]
set_instance_assignment -name IO_STANDARD LVTTL -to header\[29\]
set_instance_assignment -name IO_STANDARD LVTTL -to header\[2\]
set_instance_assignment -name IO_STANDARD LVTTL -to header\[30\]
set_instance_assignment -name IO_STANDARD LVTTL -to header\[31\]
set_instance_assignment -name IO_STANDARD LVTTL -to header\[3\]
set_instance_assignment -name IO_STANDARD LVTTL -to header\[4\]
set_instance_assignment -name IO_STANDARD LVTTL -to header\[5\]
set_instance_assignment -name IO_STANDARD LVTTL -to header\[6\]
set_instance_assignment -name IO_STANDARD LVTTL -to header\[7\]
set_instance_assignment -name IO_STANDARD LVTTL -to header\[8\]
set_instance_assignment -name IO_STANDARD LVTTL -to header\[9\]
set_instance_assignment -name IO_STANDARD LVTTL -to led\[0\]
set_instance_assignment -name IO_STANDARD LVTTL -to led\[1\]
set_instance_assignment -name IO_STANDARD LVTTL -to led\[2\]
set_instance_assignment -name IO_STANDARD LVTTL -to led\[3\]
set_instance_assignment -name IO_STANDARD LVDS -to rsds\[0\]
set_instance_assignment -name IO_STANDARD LVDS -to rsds\[1\]
set_instance_assignment -name IO_STANDARD LVDS -to rsds\[2\]
set_instance_assignment -name IO_STANDARD LVDS -to rsds\[3\]
set_instance_assignment -name IO_STANDARD LVDS -to rsds\[4\]
set_instance_assignment -name IO_STANDARD LVDS -to rsds\[5\]
set_instance_assignment -name IO_STANDARD LVDS -to rsds\[6\]
set_instance_assignment -name IO_STANDARD LVDS -to rsds\[7\]
set_instance_assignment -name IO_STANDARD LVDS -to rsds\[8\]
set_instance_assignment -name IO_STANDARD LVDS -to rsds_clk
set_instance_assignment -name IO_STANDARD LVTTL -to rsds_start
set_instance_assignment -name IO_STANDARD LVTTL -to rx_pclk_out
set_instance_assignment -name IO_STANDARD LVDS -to sdi_rx
set_instance_assignment -name IO_STANDARD LVDS -to sdi_tx
set_instance_assignment -name IO_STANDARD LVTTL -to switch\[0\]
set_instance_assignment -name IO_STANDARD LVTTL -to switch\[1\]
set_instance_assignment -name IO_STANDARD LVTTL -to switch\[2\]
set_instance_assignment -name IO_STANDARD LVTTL -to switch\[3\]
set_instance_assignment -name IO_STANDARD LVTTL -to switch\[4\]
set_instance_assignment -name IO_STANDARD LVTTL -to switch\[5\]
set_instance_assignment -name IO_STANDARD LVTTL -to switch\[6\]
set_instance_assignment -name IO_STANDARD LVTTL -to switch\[7\]
set_instance_assignment -name IO_STANDARD LVTTL -to tx_pclk_out
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL

# Timing Analysis Assignments
# ===========================
set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 500
set_global_assignment -name MAX_SCC_SIZE 50

# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<NONE>"

# Assembler Assignments
# =====================
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON
set_global_assignment -name STRATIX_JTAG_USER_CODE 04F23F03
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE EPC2
set_global_assignment -name EXCALIBUR_CONFIGURATION_DEVICE EPC2
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE EPC2
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE EPC1
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE EPC2
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE EPCS1
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPC2

# Simulator Assignments
# =====================
set_global_assignment -name START_TIME 0NS
set_global_assignment -name POWER_ESTIMATION_START_TIME "0 NS"
set_global_assignment -name GLITCH_INTERVAL 1NS

# Design Assistant Assignments
# ============================
set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF
set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF
set_global_assignment -name ASSG_CAT OFF
set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF
set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF
set_global_assignment -name CLK_CAT OFF
set_global_assignment -name CLK_RULE_COMB_CLOCK OFF
set_global_assignment -name CLK_RULE_INV_CLOCK OFF
set_global_assignment -name CLK_RULE_GATING_SCHEME OFF
set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF
set_global_assignment -name CLK_RULE_MIX_EDGES OFF
set_global_assignment -name RESET_CAT OFF
set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF
set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF
set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF
set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF
set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF
set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF
set_global_assignment -name TIMING_CAT OFF
set_global_assignment -name TIMING_RULE_SHIFT_REG OFF
set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF
set_global_assignment -name NONSYNCHSTRUCT_CAT OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF
set_global_assignment -name SIGNALRACE_CAT OFF
set_global_assignment -name ACLK_CAT OFF
set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF
set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF
set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF
set_global_assignment -name HCPY_CAT OFF
set_global_assignment -name HCPY_VREF_PINS OFF

# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP off
set_global_assignment -name USE_SIGNALTAP_FILE debug.stp

# LogicLock Region Assignments
# ============================
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT off
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_FILE atom_netlists/sdsdi_rxtx_cyclone_board.vqm

# --------------------
# start CLOCK(rx_pclk)

	# Timing Assignments
	# ==================
	set_global_assignment -name DUTY_CYCLE 50 -section_id rx_pclk
	set_global_assignment -name FMAX_REQUIREMENT "135.0 MHz" -section_id rx_pclk
	set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id rx_pclk

# end CLOCK(rx_pclk)
# ------------------

# ---------------------------------------
# start EDA_TOOL_SETTINGS(eda_simulation)

	# EDA Netlist Writer Assignments
	# ==============================
	set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id eda_simulation
	set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_simulation
	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
	set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation

# end EDA_TOOL_SETTINGS(eda_simulation)
# -------------------------------------

# --------------------------------------
# start ENTITY(sdsdi_rxtx_cyclone_board)

	# Timing Assignments
	# ==================
	set_instance_assignment -name CLOCK_SETTINGS rx_pclk -to "sdsdi_rxtx:u_demo\|freq_trans:u_freq_trans\|sclk_out~reg0"

	# Fitter Assignments
	# ==================
	set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "sdsdi_rxtx:u_demo\|freq_trans:u_freq_trans\|sclk_out~reg0"

	# ------------------------------------
	# start LOGICLOCK_REGION(oversampling)

		# LogicLock Region Assignments
		# ============================
		set_global_assignment -name LL_ORIGIN LAB_X1_Y17 -section_id oversampling
		set_global_assignment -name LL_AUTO_SIZE OFF -section_id oversampling
		set_global_assignment -name LL_HEIGHT 4 -section_id oversampling
		set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id oversampling
		set_global_assignment -name LL_RESERVED OFF -section_id oversampling
		set_global_assignment -name LL_SOFT OFF -section_id oversampling
		set_global_assignment -name LL_STATE LOCKED -section_id oversampling
		set_global_assignment -name LL_WIDTH 8 -section_id oversampling
		set_instance_assignment -name LL_MEMBER_OF oversampling -to "sdsdi_rxtx:u_demo\|sdsdi_io_interface:u_io_interface\|gxb_rxsample:u_rxsample" -section_id oversampling
		set_instance_assignment -name LL_MEMBER_OF oversampling -to "sdsdi_rxtx:u_demo\|sdsdi_io_interface:u_io_interface\|s2p:u_s2p" -section_id oversampling

	# end LOGICLOCK_REGION(oversampling)
	# ----------------------------------

# end ENTITY(sdsdi_rxtx_cyclone_board)
# ------------------------------------